Fujitsu MB88121 Application Note
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Fujitsu MB88121 Application Note

Fujitsu MB88121 Application Note

32-bit microcontroller
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Summary of Contents for Fujitsu MB88121

  • Page 1 The following document contains information on Cypress products.
  • Page 2 Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where...
  • Page 3 Fujitsu Microelectronics Europe MCU-AN-300016-E-V10 Application Note FR FAMILY 32-BIT MICROCONTROLLER MB88121, MB91460 INTERFACING MB91460 TO MB88121 APPLICATION NOTE...

  • Page 4: Revision History

    Interfacing MB91460 TO MB88121 Revision History Revision History Date Issue V1.0, MSt 2008-03-28 First draft This document contains 56 pages. MCU-AN-300016-E-V10 - 2 - © Fujitsu Microelectronics Europe GmbH...

  • Page 5: Warranty And Disclaimer

    Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in original packing and without further defects resulting from the customer´s use or the transport.

  • Page 6: Table Of Contents

    Interfacing MB91460 TO MB88121 Contents Contents REVISION HISTORY ......................2 WARRANTY AND DISCLAIMER ..................3 CONTENTS .......................... 4 1 INTRODUCTION......................6 2 HARDWARE ........................7 Power supply......................7 Reset........................8 Clock connection ..................... 8 2.3.1 MCU Clock ....................8 2.3.2 CC Clock ....................
  • Page 7 3.1.4.1 Port function register settings in start91460.asm...... 30 3.1.5 External bus clock..................34 3.1.5.1 Example setting in start91460.asm .......... 34 3.1.6 Initialisation sequence of MB88121 ............35 Interrupts....................... 36 3.2.1 MB88121 interrupt ................... 36 3.2.2 MCU external interrupt................37 3.2.2.1 External interrupt configuration registers........

  • Page 8: Introduction

    1 Introduction FUJITSU Microelectronics Europe GmbH offers a stand alone FlexRay Communication Controller, MB88121 series, which supports parallel and serial connectivity to Host MCU. The MB88121 series supports two parallel Bus interface modes, 16-bit none-multiplexed and 16-bit multiplexed mode, for the 32-bit MB91460 series. The following discusses Hardware and Software requirement based on MB91F467D series.

  • Page 9: Hardware

    3V—5.5V Table 2-1 MB91F467D power supply pins The MB88121 series is using single voltage supply. All pins having the same voltage level which are supplied at Vcc pins. In case of using the interrupt functionality the interrupt pins of MB88121 and the input pins (e.g. external interrupt) have same voltage level, if not level conversion via level shifter is required.

  • Page 10: Reset

    MB88121 via IO port. The example in this Application Note is using first mentioned approach. As MB88121 series is a single voltage supply series, care have to be taken in case the MB91F467D series is using different voltage supply level at bus interface pins (Vdd35) and other IO pins (Vdd).
  • Page 11 Interfacing MB91460 TO MB88121 Chapter 2 Hardware Figure 2-1 Memory map of internal ROM external bus mode © Fujitsu Microelectronics Europe GmbH - 9 - MCU-AN-300016-E-V10...

  • Page 12: Cc Operation Mode

    Interfacing MB91460 TO MB88121 Chapter 2 Hardware 2.4.2 CC operation mode The mode pins MD[2:0] and MDE[2:0] select between different bus types. These pins can directly connected to GND or Vcc. 2.4.2.1 None multiplexed bus interface mode MD2 MD1 Mode...

  • Page 13: 16-Bit None Multiplexed Mode

    Interfacing MB91460 TO MB88121 Chapter 2 Hardware 2.5.1 16-bit none multiplexed mode External bus interface: MB88121 pins in connection with MCU MB91F467D pins CC pin Nr Name Function MCU pin Nr Name P06_2/A10 P06_1/A9 P06_0/A8 P07_7/A7 P07_6/A6 Address bus P07_5/A5 MCU=>CC...

  • Page 14: 16-Bit Multiplexed Bus Interface Mode

    Interfacing MB91460 TO MB88121 Chapter 2 Hardware 2.5.2 16-bit multiplexed bus interface mode External bus interface: CC pins in connection with MCU pins CC pin Nr Name Function MCU pin Nr Name AD10 P00_2/D26 P00_1/D25 P00_0/D24 P01_7/D23 P01_6/D22 Address/data bus...

  • Page 15: Interrupts

    Table 2-9 CC interrupt output by 16bit non-multiplexed mode 2.7 DMA pins The MB88121 is supporting DMA transfer from Host MCU. For this reason the DMA_Req pin is available. This pin needs to be connected to a DMA request pin at MCU side. For MB91F467D it is DREQ0 pin.

  • Page 16: Debug Pins

    Interfacing MB91460 TO MB88121 Chapter 2 Hardware 2.9 Debug pins The MB88121 including debug pins, which help debugging during development phase. CC debug pins CC pin Nr Name Function I/O type Configuration register Start of dynamic segment CYCS0 Cycle 0 start...

  • Page 17: Software

    This chapter discusses the Software related issues 3.1 Bus interface setup To access the MB88121 register in application these registers needs to be visible in the MCU address range. For that reason the bus interface needs to be setup. All these settings are available in start91460.asm file for MB91460 series MCU.
  • Page 18 BCLK pin and the valid data is output from the pins D[15:0]. 4. When the RD pin becomes high level again, the read access is finished. Pins D[15:0] become Hi-Z. Figure 3-2 MB88121 Write operation (non-multiplexed) Operation sequence: 1. The WR pin (signal ) becomes low level.

  • Page 19: Simplified Timing Diagram Of Mb88121B (Multiplexed Access)

    3.1.2 Simplified timing diagram of MB88121B (multiplexed access) Following timing needs to be setup in MB91460 series when using 16-bit multiplexed access. Figure 3-3 MB88121 read operation (multiplexed mode) Operation sequence: 1. The address is latched by the rising edge of AS pin (signal 2.
  • Page 20 Interfacing MB91460 TO MB88121 Chapter 3 Software Figure 3-4 MB88121 write operation (multiplexed) Operation sequence: 1. The address is latched by the rising edge of AS pin (signal 2. The WR pin (signal ) becomes low level. At the next rising edge of the BCLK pin the data on the pins D[15:11] and AD[10:0] is written to a temporary register and the RDY pin becomes low level, which causes the MCU to wait.

  • Page 21: Configuration Registers Of The External Bus Interface

    Interfacing MB91460 TO MB88121 Chapter 3 Software 3.1.3 Configuration registers of the external bus interface The following table list the external bus interface register available in MB91F467D series. Address Area select register Area configuration register 0x000640 ASR0 ACR0 0x000644 ASR1...

  • Page 22: Area Configuration Register (Acr)

    Interfacing MB91460 TO MB88121 Chapter 3 Software 3.1.3.2 Area Configuration Register (ACR) Function of register ACR is listed below. The register defines e.g. Data bus width, bus signal usage, etc. A full description can be found in MB91460 series Hardware Manual.
  • Page 23 Interfacing MB91460 TO MB88121 Chapter 3 Software ASZ[3] ASZ[2] ASZ[1] ASZ[0] Area size Valid bit of register ASR 512MB ASR_A[31:29] 1024MB ASR_A[31:30] 2048MB ASR_A[31] Grey: used for MB88121B Table 3-3 ASZ bits of register ACR TYP[3] TYP[2] TYP[1] TYP[0] Access type...

  • Page 24: Area Wait Register (Awr)

    Interfacing MB91460 TO MB88121 Chapter 3 Software DBW1 DBW0 Data bus width 8bit 16bit 32bit BST1 BST0 Maximum burst length Single access (not burst access) One access sequence starts with an assertion of and ends with negation of Burst access (transfer successive data items in one access sequence) RDY input is ignored in burst access.
  • Page 25 Interfacing MB91460 TO MB88121 Chapter 3 Software ACR_TYP[3:0]=00XX Pre- Normal access (asynchronous SRAM, I/O, and single/page/burst-ROM/FLASH) condition ACR_TYP[3:0]=01XX Address/data multiplexed access (8/16-bit bus width only) AWR Bit Function is asserted at the same time when is asserted is asserted at the rising edge of the clock signal MCLK...

  • Page 26: Timing Example Of Ordinary (Non-Multiplexed) Bus

    Interfacing MB91460 TO MB88121 Chapter 3 Software 3.1.3.4 Timing example of ordinary (non-multiplexed) bus Using the settings above the timing should look like following figure: An example under the condition ACR_TYP[3:0]=3 and AWR=0x2008 is shown below. Figure 3-5 Timing example of the non-multiplexed mode Note: •...

  • Page 27: Timing Example Of Multiplexed Bus

    Interfacing MB91460 TO MB88121 Chapter 3 Software 3.1.3.5 Timing example of multiplexed bus An example with configuration ACR_TYP[3:0]=7 and AWR=0x0008 is shown below. Figure 3-6 Timing example of the multiplexed bus mode Note: • The basic access cycle includes 2 address output cycles and 1 data cycle.

  • Page 28: Settings Of Register Asr, Awr, Acr, Cser In File Start91460.Asm

    Interfacing MB91460 TO MB88121 Chapter 3 Software 3.1.3.6 Settings of register ASR, AWR, ACR, CSER in file start91460.asm Using the Fujitsu template projects, the bus interface settings are defined in the start91460.asm file. Following shows the according settings in the file. ;=============================== ;...

  • Page 29: Register Cher, Iowr, Tcr, Mcra, Mcrb And Rcr

    Interfacing MB91460 TO MB88121 Chapter 3 Software 3.1.3.7 Register CHER, IOWR, TCR, MCRA, MCRB and RCR Register CHER decides whether the data, read from the chip select area, is saved in the built-in cache or not. For the communication controller the cache function is disabled through register ICHCR.

  • Page 30: Setup Of Port Function Register (Pfr)

    Interfacing MB91460 TO MB88121 Chapter 3 Software Note: Not all MB91460 devices support Cache on external bus interface. 3.1.4 Setup of Port function register (PFR) The Port function register defines which resource of the MCU is connected to the pin.
  • Page 31 Interfacing MB91460 TO MB88121 Chapter 3 Software Since the communication controller MB88121B has 11bit address-line and 16bit data-line, the bus width is fixed. • 16bit data bus, MCU pin D15 to D0 are not used (Big endian Byte ordering). •...

  • Page 32: Port Function Register Settings In Start91460.Asm

    Interfacing MB91460 TO MB88121 Chapter 3 Software 3.1.4.1 Port function register settings in start91460.asm Following find the settings required in the start91460.asm file to enable the corresponding function at the pin. ;=============================================== ; 4.9.9 Select External bus mode (Data lines) ;===============================================...
  • Page 33 Interfacing MB91460 TO MB88121 Chapter 3 Software ;=================================================== ; 4.9.11 Select External bus mode (Control lines) ;=================================================== #set PFUNC8 B'10010000 ;select control signals ||||||||__ WRX0 / P08_0 |||||||___ WRX1 / P08_1 ||||||____ WRX2 / P08_2 |||||_____ WRX3 / P08_3 ||||______...
  • Page 34 Interfacing MB91460 TO MB88121 Chapter 3 Software ;================================================================== ; 6.6.12.9 set PFR08 Register. External bus mode (Control Signals) ;================================================================== #0x0D88, R1 ; Port 8 Function Register, (PFR08) #PFUNC8, R0 ; load port settings R0, @R1 ; set register ;==================================================================== ; 6.6.12.10 set PFR09 Register. External bus mode (Control Signals) ;====================================================================...
  • Page 35 Interfacing MB91460 TO MB88121 Chapter 3 Software 3.1.4.1.1 Multiplexed mode port function register setting Using Multiplexed mode lower pin count is required because of Multiplexed address- data bus usage. In Multiplexed mode ASX signal is required. Find the different port function setting below: ;====================================================...

  • Page 36: External Bus Clock

    To finalise the bus interface settings the external Bus clock needs to be setup. This clock is output at MCLKO pin. The maximum bus clock frequency at MB88121 side is 33MHz. Based on a 4MHz external oscillator and internal PLL circuitry the maximal core frequency of MB91F467D (CLKB) can reach 96MHz.

  • Page 37: Initialisation Sequence Of Mb88121

    FlexRay CC with clock the STOP bit needs to be set to ‘0’. Other bits shall be set to ‘0’. The stabilisation time of the PLL is 600us. After this time the MB88121 The PLL clock usage can be selected via the CCNT.SEEL bit ( set to ‘1’).

  • Page 38: Interrupts

    That requires also the setup of the external interrupt at MCU beside the setup of the interrupt at MB88121 side. 3.2.1 MB88121 interrupt Depending on used bus interface mode the MB88121 have different interrupt pins available. CC pin Interrupt type...

  • Page 39: Mcu External Interrupt

    Status Interrupt Enable Set / Reset (SIES, SIER) : Enable / disable status interrupts • Interrupt Line Enable (ILE): Enable interrupt lines 3.2.2 MCU external interrupt Following show the setup and usage of the external interrupt (rising edge) for MB88121 connection. Following registers are relevant for external interrupt: •...

  • Page 40: Port Function Register (Pfr)

    Interfacing MB91460 TO MB88121 Chapter 3 Software Description Detect “L” level and generate an interrupt request Detect “H” level and generate an interrupt request Detect the rising-edge and generate an interrupt request Detect the falling-edge and generate an interrupt request Table 3-14 ELVR register CC interrupt pins are high-level active.
  • Page 41 Interfacing MB91460 TO MB88121 Chapter 3 Software MCU pin Nr Pin function precondition P24_0 General purpose I/O PFR24_0=0 DDR24_0=0/1 INT0 External interrupt 0 PFR24_0=1 DDR24_0=0 P24_1 General purpose I/O PFR24_1=0 DDR24_1=0/1 INT1 External interrupt 1 PFR24_1=1 DDR24_1=0 P24_2 General purpose I/O...

  • Page 42: Interrupt Vector Table

    Interfacing MB91460 TO MB88121 Chapter 3 Software Table 3-17 I/O port configuration for external interrupt An initialization example of the external interrupt 5 is shown below. void Init_extint_5 (void){ ENIR0_EN5 = 0; /* disable extInt5 interrupt */ DDR24_D5 = 0;...
  • Page 43 Interfacing MB91460 TO MB88121 Chapter 3 Software Interrupt level Interrupt vector External Interrupt interrupt number Configuration Register Default vector channel (decimal) Offset register address address 0x384 0x000FFF84 ICR07 0x447 reserved 0x380 0x000FFF80 Table 3-18 Interrupt vector table A default interrupt vector table for MB91460 series is located in file vectors.c (provided in the template project).

  • Page 44: Dma Usage

    For further details see Hardware Manual of MB91460 series and Application note mcu-an- 300059-e-mb91460_dma. Using the DMA following needs to be encountered: The MB88121 is connected to the external transfer request pin “DREQ0” in our example. So this DMA bus interface transfer needs to be setup. Following settings have to be selected:...

  • Page 45: Dma Flow For Output Buffer Transfer

    Interfacing MB91460 TO MB88121 Chapter 3 Software 3.3.3 DMA flow for Output buffer transfer Figure 3-7: Output buffer DMA flow © Fujitsu Microelectronics Europe GmbH - 43 - MCU-AN-300016-E-V10...

  • Page 46: Dma Flow For Input Buffer Transfer

    Interfacing MB91460 TO MB88121 Chapter 3 Software 3.3.4 DMA flow for input buffer transfer Figure 3-8 Input buffer DMA flow MCU-AN-300016-E-V10 - 44 - © Fujitsu Microelectronics Europe GmbH...

  • Page 47: Debugging Support

    Interfacing MB91460 TO MB88121 Chapter 3 Software 3.4 Debugging support The MB88121 offering also debug support at some pins. CC debug pins CC pin Nr Name Function I/O type Configuration register Start of dynamic segment CYCS0 Cycle 0 start CYCS...

  • Page 48: Reference

    Interfacing MB91460 TO MB88121 Chapter 4 Reference 4 Reference • Application note: mcu-an-300021-e-start91460 describing start91460.asm file • Application note: mcu-an-300033-e-mb91460_hw_setup • Application note: mcu-an-300055-e-mb91460_irq • Application note: mcu-an-300059-e-mb91460_dma • MB91F467D series Datasheet • Hardware Manual for MB91460 series • MB88121B series Datasheet •...

  • Page 49: Appendix

    5.1 Connection example using none-multiplexed Bus interface A connection example of the non-multiplexed mode is summarized in the following table. The gray entries show the differences between two parallel modes. All pins of the MB88121 communication controller (CC) are divided into 7 categories: •...
  • Page 50 Interfacing MB91460 TO MB88121 Chapter 5 Appendix External bus interface: MB88121 pins in connection with MCU MB91F467D pins CC pin Nr Name Function MCU pin Nr Name P06_2/A10 P06_1/A9 P06_0/A8 P07_7/A7 P07_6/A6 Address bus P07_5/A5 MCU=>CC P07_4/A4 P07_3/A3 P07_2/A2 P07_1/A1...
  • Page 51 Interfacing MB91460 TO MB88121 Chapter 5 Appendix Write enable P10_3/WEX Ready signal P08_7/RDY CC=>MCU DMA_REQ DMA request P13_0/DREQ0 CC mode pins CC pin Nr Name Function I/O type Logic value Mode selection 16bit parallel bus interface MDE2 Extended mode Non-multiplexed mode...
  • Page 52 Interfacing MB91460 TO MB88121 Chapter 5 Appendix Figure 5-1 Schematic view of the non-multiplexed mode MCU-AN-300016-E-V10 - 50 - © Fujitsu Microelectronics Europe GmbH...

  • Page 53: Connection Example Using Multiplexed Bus Interface

    Interfacing MB91460 TO MB88121 Chapter 5 Appendix 5.2 Connection example using multiplexed bus interface A connection example of the multiplexed mode is summarized in the following table. The gray entries show the differences between two parallel modes. All pins of the communication controller (CC) are divided into 7 categories: •...
  • Page 54 Interfacing MB91460 TO MB88121 Chapter 5 Appendix External bus interface: CC pins in connection with MCU pins CC pin Nr Name Function MCU pin Nr Name AD10 P00_2/D26 P00_1/D25 P00_0/D24 P01_7/D23 P01_6/D22 Address/data bus P01_5/D21 P01_4/D20 P01_3/D19 P01_2/D18 P01_1/D17 P01_0/D16...
  • Page 55 Interfacing MB91460 TO MB88121 Chapter 5 Appendix MDE2 Extended mode Multiplexed mode MDE1 selection for MB91460 MDE0 CC debug pins CC pin Nr Name Function I/O type Configuration register Start of dynamic segment CYCS0 Cycle 0 start CYCS Cycle start...
  • Page 56 Interfacing MB91460 TO MB88121 Chapter 5 Appendix Figure 5-2 Schematic view of the multiplexed mode MCU-AN-300016-E-V10 - 54 - © Fujitsu Microelectronics Europe GmbH...

  • Page 57: Tables

    Table 5-2 16bit multiplexed mode ..................53 5.4 Figures Figure 2-1 Memory map of internal ROM external bus mode ..........9 Figure 3-1 MB88121 read operation (non-multiplexed) ............15 Figure 3-2 MB88121 Write operation (non-multiplexed) ............16 MCU-AN-300016-E-V10 - 55 -...
  • Page 58 Interfacing MB91460 TO MB88121 Chapter 5 Appendix Figure 3-3 MB88121 read operation (multiplexed mode)............17 Figure 3-4 MB88121 write operation (multiplexed) ............... 18 Figure 3-5 Timing example of the non-multiplexed mode ............. 24 Figure 3-6 Timing example of the multiplexed bus mode ............. 25 Figure 3-7: Output buffer DMA flow..................

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