Fujitsu MB91460 SERIES FR60 User Manual page 830

Chapter 39 Programmable Pulse Generator
7.Q & A
7.5 What count clocks are available and how are they selected?
Count clock selection
The count clock is selectable out of the four choices listed below.
Use the count clock selection bit (PCN.CKS[1:0]).
Count Clock Selection Bit
Count
Clock
CLKP
CLKP/4
CLKP/16
CLKP/64
(See "8. Caution (Page
7.6 How do I clamp the PPG pin output level?
PPG output mask selection
The level of PPG pin output can be clamped.
Use the PPG Output Mask Selection bit (PCN.PGMS) and the duty value (PDUT) to set.
PPG Pin Output
To clamp the "L" level under normal polarity
To clamp the "H" level under normal polarity
To clamp the "H" level under inverted polarity
To clamp the "L" level under inverted polarity
PPG pin output can be set to all "L". (when OSEL="0")
PPG
Reduce
the duty
value
PPG pin output can be set to all "H". (when OSEL="0")
PPG
Reduce
the duty value
PPG output will also equal all "H" if "0" is set in both the PPG Period Setting Register (PCSR) and PPG Duty
Setting Register (PDUT). (when OSEL="0")
814
CKS1 CKS0
0 0
0 1
1 0
1 1
No.821)".)
PPG Output Polarity
(Example) CLKP = 32 MHz
Count Clock
32MHz
8MHz
2MHz
500kHz
Specification
Bit (OSEL)
Set the PPG Output Mask Selection bit
When "0"
When "0"
Set the PPG Output Mask Selection bit
When "1"
When "1"
Write "1" to PGMS (mask bit) on occurrence
of an interrupt caused by a borrow.
If "0" is written to PGMS on occurrence of
an interrupt caused by a borrow, a PWM
waveform can be generated without
incurring hazard output.
Write the same value as the cycle setting
register value to the duty setting register
on occurrence of an interrupt caused by
a compare match.
Period (1 - FFFFh)
62.5ns - 2.048µs
250ns - 8.192µs
1µs - 32.76ms
4µs - 131.0ms
Setting Procedure
(PGMS) to "1".
Period value (PCSR) =
Set a duty value (PDUT).
(PGMS) to "1".
Period value (PCSR) =
Set a duty value (PDUT).