Fujitsu MB91460 SERIES FR60 User Manual page 436

32-bit microcontroller
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Chapter 29 MPU / EDSU
4.Registers
Table 4-3 Relationship of BCR, BAD and BIRQ registers
Group Config
BCR3
BCR4
BCR5
BCR6
BCR7
Group of Channels, Permission Definition Register
The permission definition registers are valid only for the group of channels operating in MPU mode. This is the case
if MPE is set to '1'. If the group does not operate in MPU mode, the permission configuration is not required (don't
care).
Normally MPU channels operate in range mode for the address definitions.
The type of the permission, which could be set-up, depends on the comparator type configuration (CTC) for each
comparator pair. MPU channels could be configured either to check instruction addresses (IA) or operand address-
es (OA). IA ranges could be used to define exceute permissions. OA ranges could be used to define read and write
permissions.
The comparator type for MPU usage could be set to
CTC=0: both IA ranges define execute permissions,
CTC=1: both OA ranges define read/write permissions and
420
Address/Data
BADx Usage
Point0, Mask0
BAD12
Point1
BAD13
Point2, Mask1
BAD14
Point3
BAD15
Point0, Mask0
BAD16
Point1
BAD17
Point2, Mask1
BAD18
Point3
BAD19
Point0, Mask0
BAD20
Point1
BAD21
Point2, Mask1
BAD22
Point3
BAD23
Point0, Mask0
BAD24
Point1
BAD25
Point2, Mask1
BAD26
Point3
BAD27
Point0, Mask0
BAD28
Point1
BAD29
Point2, Mask1
BAD30
Point3
BAD31
Point
Mask
Combination
EP0
EM0
range 0
ER0
EP1
EP2
EM1
range 1
ER1
EP3
EP0
EM0
range 0
ER0
EP1
EP2
EM1
range 1
ER1
EP3
EP0
EM0
range 0
ER0
EP1
EP2
EM1
range 1
ER1
EP3
EP0
EM0
range 0
ER0
EP1
EP2
EM1
range 1
ER1
EP3
EP0
EM0
range 0
ER0
EP1
EP2
EM1
range 1
ER1
EP3
BIRQ
BD12
OA0
OA1
BD13
BD14
DT0
DT1
BD15
OA0
BD16
BD17
OA1
DT0
BD18
BD19
DT1
OA0
BD20
BD21
OA1
DT0
BD22
BD23
DT1
OA0
BD24
BD25
OA1
DT0
BD26
BD27
DT1
OA0
BD28
OA1
BD29
BD30
DT0
DT1
BD31

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