Fujitsu MB91460 SERIES FR60 User Manual page 354

Chapter 26 DMA Controller
2.DMA Controller (DMAC) Registers
[Bits 28 to 24] IS4 to 0 (Input Select)*: Transfer source selection
These bits select the source of a transfer request note that the software transfer request by the STRG bit
function is always valid regardless of the setting of these bits. As listed in
Request Sources".
Table 2-1 Settings for Transfer Request Sources
IS EIS RN
00000 - -
00001
- - -
01101
01110 - -
01111 - -
10000 0000 0
10001 0000 1
10010 0000 2
10011 0000 3
10100 0000 4
10101 0000 5
10110 0000 6
10111 0000 7
11000 0000 8
11001 0000 9
11010 0000 10
11011 0000 11
11100 0000 12
11101 0000 13
11110 0000 14
11111 0000 15
• When reset: IS4-0 is initialized to 00000
• When reset: EIS3-0 is initialized to 0000
• These bits are readable and writable.
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Function
Activation by hardware prohibited
Setting prohibited
-
Setting prohibited
External DMA-pin high level or rising edge
External DMA-pin low level or falling edge
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
Reload Timer 0
Reload Timer 1
USART (LIN) 0 RX
USART (LIN) 0 TX
USART (LIN) 1 RX
USART (LIN) 1 TX
USART (LIN, FIFO) 4 RX
USART (LIN, FIFO) 4 TX
USART (LIN, FIFO) 5 RX
USART (LIN, FIFO) 5 TX
A/D Converter
Programmable Pulse Generator (PPG) 0
.
B
.
B
Table 2-1 "Settings for Transfer
Transfer stop request
not available
-
-
-
-
-
-
available
-
available
-
available
-
available
-
-
-