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Chapter 29 MPU / EDSU
4.Registers
BIT[19]: URX1 - User Read/eXecute permission register for range 1
Setting valid for CTC == 0 (Instruction address range comparator):
0
User has no execute permission on address range 1(default)
1
User has execute permission on address range 1
Setting valid for CTC == 1 or CTC == 2 (Operand address range comparator):
0
User has no read permission on address range 1 (default)
1
User has read permission on address range 1
BIT[18]: UW1 - User Write permission register for range 1
Setting valid for CTC == 1 or CTC == 2 (Operand address range comparator):
0
User has no write permission on address range 1 (default)
1
User has write permission on address range 1
BIT[17]: URX0 - User Read/eXecute permission register for range 0
Setting valid for CTC == 0 or CTC == 2 (Instruction address range comparator):
0
User has no execute permission on address range 0 (default)
1
User has execute permission on address range 0
Setting valid for CTC == 1 (Operand address range comparator):
0
User has no read permission on address range 0 (default)
1
User has read permission on address range 0
BIT[16]: UW1 - User Write permission register for range 0
Setting valid for CTC == 1 (Operand address range comparator):
0
User has no write permission on address range 0 (default)
1
User has write permission on address range 0
Group of Channels, Mode Configuration Register
BIT[15]: MPE - Memory Protection Enable
0
The group of channels operates as debug interface and defines breakpoints (default)
422
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