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[Bits 18 to 16] DSS2 to 0 (DMA Stop Status)*: Transfer stop source indication
These bits indicate a code (end code) of 3 bits that indicates the source of stopping or termination of DMA
transfer on the corresponding channel. For a list of end codes, see
Table 2-6 End Codes
DSS
000
Initial value
B
x01
Address error (underflow/overflow)
B
x10
Transfer stop request
B
x11
Normal end
B
DMA stopped temporarily (due, for example, to
1xx
B
DMAH, PAUS bit, and an interrupt)
A transfer stop request is set only when it is requested by a peripheral device or the external pin DSTP function is
used.
The Interrupt column indicates the type of interrupts that can occur.
•
When reset: Initialized to 000
•
These bits can be cleared by writing 000
•
These bits are readable and writable. Note that the only valid written value is 000.
[Bits 15 to 8] SASZ (Source Addr count SiZe)*: Transfer source address count size specification
These bits specify the increment or decrement width for the transfer source address (DMASA) of the
corresponding channel in each transfer operation. The value set by these bits becomes the address
increment/decrement for each transfer unit. The address increment/decrement conforms to the instruction in
the transfer source address count mode (SADM).
SASZ
XX
Specify the increment/decrement width of the transfer source address. 0 to 255
H
•
When reset: Not initialized
•
These bits are readable and writable.
Function
.
B
to them.
B
Function
2.DMA Controller (DMAC) Registers
Table
2-6"End Codes".
Interrupt
None
Error
Error
End
None
Chapter 26 DMA Controller
349
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