Fujitsu MB91460 SERIES FR60 User Manual page 550

Chapter 31 External Bus
2.External Bus Interface Registers
[Bits 27-24, 19-16, 11-8] IW03-00,IW13-10 (I/O Access Wait)
These bits set the number of auto-wait cycles for I/O access during DMA fly-by access.
Table 2-23 "Settings for the Number of I/O Wait Cycles" lists the settings for the number of I/O wait cycles.
Table 2-23 Settings for the Number of I/O Wait Cycles
IWn3 IWn2
0 0
0 0
1 1
Because data is synchronized between the transfer source and transfer destination, the I/O side setting of the
IWnn bits and the wait setting for the fly-by transfer destination (such as memory), whichever is larger, is used as
the number of wait cycles to be inserted. Consequently, more wait cycles than specified by the IWnn bits may be
inserted.
2.7 Chip Select Enable Register (CSER)
Because data is synchronized between the transfer source and transfer destination, the I/O side
setting of the IWnn bits and the wait setting for the fly-by transfer destination (such as memory),
whichever is larger, is used as the number of wait cycles to be inserted. Consequently, more
wait cycles than specified by the IWnn bits may be inserted.
■ Configuration of the Chip Select Enable Register (CSER)
The chip select enable register (CSER: Chip Select Enable register) enables and disables each chip select area.
Figure 2-7 "Configuration of the Chip Select Enable Register (CSER)" shows the configuration of the chip select
enable register (CSER).
Figure 2-7 Configuration of the Chip Select Enable Register (CSER)
31
00000680 CSE7 CSE6 CSE5 CSE4 CSE3 CSE2 CSE1 CSE0 00000001
H
■ Functions of Bits in the Chip Select Enable Register (CSER)
The following explains the functions of the bits in the chip select enable register (CSER).
[Bits 31-24] CSE7-0 (Chip Select Enable 0-7)
These bits are the chip select enable bits for CS0-CS7.
The initial value is 00000001
When 1 is written, a chip select area operates according to the settings of ASR0-7, ACR0-7, and AWR0-7.
534
IWn1 IWn0
0 0
0 1
...
1 1
30 29 28 27
, which enables only the CS0 area.
B
Number of I/O wait cycles
0 cycle
1 cycle
...
15 cycle
26 25 24
Initial value
INIT RST
00000001
B B
Access
R/W