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Chapter 11 Memory Controller
8.Explanations of Registers
• BIT[4]: PFMC - Prefetch Miss Cache enable
0
Standard cache algorithm (default)
1
Prefetch misses are cached only
This bit is cleared after reset. The prefetch miss cache is disabled by default. The instruction cache uses the stand-
ard algorithm of writing cache entries for each accessed instruction word from FLASH.
Setting the PFMC bit switches to a second write algorithm for cache entries. This algorithm writes only this instruc-
tion words to the cache, which are causing prefetch miss conditions.
The FR CPU requests approximately one instruction word (which contains two 16 bit instruction codes) in two clock
cycles. If the FLASH data throughput (one word in two cycles) is sufficient for the needs of the CPU, the PFMC
option is useful in most cases.
If the FLASH access time is two clock cycles, normally no wait states are generated when the next instruction word
is requested from a consecutive address and prefetch is enabled. Thus, caching such linear code segments in con-
junction with prefetch may not improve the code fetch performance, which is at the optimum already. More interest-
ing is to improve the situation for branches in the code, where prefetch could not remove the latency of accessing
it. If FPMC is set to '1', the cache algorithm stores only these FLASH accesses, which have caused a wait condition
due to a prefetch miss condition (not mached predicted address).
The effect of this algorithm is, that the restricted amount of cache entries is utilized more efficiently. Usually the
same performance can be reached with half the cache size. Or, in other words, the cache is as same efficient as it
would have the doubled size.
The efficiency of the PFMC algorithm depends on the structure of the application.
• BIT[3]: LOCK - Global lock of cache entries
0
Write of cache entries enabled (default)
1
Writing of cache entries is disabled, the cache contents is locked
This bit is cleared during reset. The cache entries are writable by default.
If the LOCK bit is set, no new entries can be written to cache memory. The old contents of cache entries remains
in memory. There is only a global lock feature for all cache entries.
• BIT[2]: ENAB - Instruction cache enable
0
The instruction cache is disabled (default)
1
Enable the instruction cache
This bit is cleared after reset. By default the instruction cache is disabled.
If the ENAB bit is set, the instruction cache is switched on. The instruction cache is dedicated to FLASH access only.
The cache is utilized by the prefetch algorithm as prefetch buffer. Hence prefetch can be used in an unbuffered form
with cache disabled.
Cache miss did not cause code fetch penalties. The FLASH access is started in parallel, independent from cache
hit or miss evaluation.
(If the cache is disabled, the cache entries and the TAG RAM contents can be accessed memory mapped. This
feature is disabled in this version of the interface, see the explanaition of the TAGE bit.)
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