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FLUSHbit is set to "0" when the cache is flushed.)
[Bit 1] LRU bit (way 1 only)
This bit exists only in the instruction cache tag in way 1. The bit indicates way 1 or 2 as the
way containing the last entry accessed in the selected set. When set to "1", the LRU bit
indicates that the entry of the set in way 1 is the last entry accessed. When set to "0", it
indicates that the one in way 2 is the last entry accessed.
[Bit 0] ETLK: Entry lock bit
This bit is used to lock all the entries in the block corresponding to the tag in the cache. When
set to "1", the entries are locked and are not updated when a cache miss occurs. Note,
however, that invalid sub-blocks are updated. If a cache miss occurs with both of ways 1 and
2 in the entry lock states, access to external memory takes place after losing one cycle used
for evaluating the cache miss.
● Control register structure
ISIZE (8 bit)
0000 03C7
H
ISIZE [bits 1 to 0] : SIZE1 and SIZE0
These bits set the cache capacity. The combination of the settings determines the cache size,
IRAM size, and the address map in RAM mode as shown in Figure I-CACHE-3. When the
cache size is changed, be sure to flush the cache and release the entry lock before turning on
the cache.
ICHCR [bits 7 to 0] :
The ICHCR (I-Cache Control Register) controls the operation of the instruction cache. Writing
a value to the ICHCR has no effect on the caching of any instruction fetched within three
cycles that follow.
ICHCR (8 bit)
7
0000 03E7
RAM
H
R/W
7
6
5
-
-
-
-
-
-
CACHE Size Register
SIZE1
SIZE0
0
0
1 KB
0
1
2 KB
1
0
4 KB (initial value)
1
1
Setting disabled
6
5
-
GBLK
-
R/W
4
3
2
-
-
-
-
-
-
Size
4
3
2
ALFL
EOLK
ELKR
R/W
R/W
R/W
Chapter 12 Instruction Cache
2.Main body structure
1
0
Initial value
---- --10
SIZE1
SIZE0
R/W
R/W
1
0
Initial value
0-00 0000
FLUSH
ENAB
R/W
R/W
B
B
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