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1
This bit is cleared by a (repeated-) start or stop condition.
[bit 0] ADT (Address Data Transfer)
This bit indicates the detection of an address data transfer.
0
1
This bit is set to '1' by a start condition. It is cleared after the second byte if a ten bit slave address header with
write access is detected, else it is cleared after the first byte.
"After" the first/second byte means:
• a '0' is written to the MSS bit during a master interrupt (MSS='1' and INT='1' in IBCR0)
• a '1' is written to the SCC bit during a master interrupt (MSS='1' and INT='1' in IBCR0)
• the INT bit is being cleared
• the beginning of every byte transfer if the interface is not involved in the current transfer as master or slave
General call address received as slave.
Incoming data is not address data (or bus is not in use).
Incoming data is address data.
Chapter 33 I2C Controller
2.I2C Interface Registers
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