Table of Contents
Advertisement
•
For the I/O device on the data output side, a read strobe of three bus cycles extended by the I/O wait cycle
and I/O hold wait cycle is generated.
•
For SDRAM/FCRAM on the receiving side, a WRIT command is issued at the timing that allows writing after
the I/O wait cycle. The I/O wait cycle may be longer depending on the SDRAM/FCRAM bank active state and
SDRAM/FCRAM wait setting.
•
The I/O hold wait cycle does not affect the write strobe. Note, however, that the CS signal is retained until the
fly - by bus access cycles end.
•
For fly - by transfer from an I/O device to SDRAM/FCRAM, be sure to set the HLD bit in the DMAC I/O wait
register (IOWR) to 1 to enable the I/O hold wait cycle.
•
Fly - by transfer must always be performed between data buses having the same bus width.
10.4 DMA Fly-By Transfer (SDRAM/FCRAM -> I/O)
This section describes the operation of DMA fly - by transfer (SDRAM/FCRAM device to I/O).
■ DMA Fly-By Transfer (SDRAM/FCRAM -> I/O)
Figure 1.10 - 4 shows an operation timing chart assuming TYP3 to TYP0 set to 1000B, AWR set to 0051H, and
IOWR set to 42H.
Chapter 31 External Bus
10.DMA Access Operation
597
Advertisement
Table of Contents
