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Chapter 41 Up/Down Counter
3.Configuration
Up/Down Counter (16 Bit Mode)
16 bit mode
M16E
UDCC0 : bit15
1
16 bit mode
CMS1-0
0
0
0
1
1
0
1
1
Peripheral clock
Prescaler
CLKP
From port data
register
CLKS
0
0
CLKP divided by 2
1
CLKP divided by 8
P20 EPFR20.0
0
Others
1
Enable UDC
AIN0/SIN2/P20.0
detection
BIN0/SOT2/P20.1
P20 EPFR20.1
0
Others
CES1-0
1
Enable UDC
Read
0
from
0
port
1 0
From port data
1 1
register
ZIN0/SCK2/P20.2
P20 EPFR20.2
0
Others
1
Enable UDC
Note: For ICR registers and interrupt vectors, refer to
838
Figure 3-3 Configuration Diagram
CDCF
UDCC0: bit14
0
No change direction
1
Direction changed
WRITE 0: Flag clear
UDCC0: bit11-10
Timer mode (Countdown only)
Up/down count mode
Activation
Phase difference count mode (Multiply by 2)
CSTR
Phase difference count mode (Multiply by 4)
0
1
Counter clear
UDCC0: bit 12
CTUT
No impact
0
0
Read from port
Data transfer
1
* Only 16 bit transfer is enabled
while counting stops.
Edge
OR
OR
Reload/compare register (Write only)
Gate
UDCC0: bit 9 -8
0
0
Disable edge detection
Enable falling edge detection
1
Enable rising edge detection
Enable both edge detection
Read from
port
Edge
detection
From port data
register
Figure 3-4 Register List
CFIE
UDCC0: bit 13
0
0
Disable interrupts
1
Enable interrupts
0
1
UDF1-0
UDF1-0
UDCS0: bit 1 -0
-
Write: Disabled, Read only
No input
0
0
0
1
Countdown
1
0
Countup
UDCS0: bit7
1
1
Both countdown and countup
Stop counting
Start counting
Up/Down Counter (Read only)
UDCR1
UDCR0
1
0
Reload
UDCC0: bit6
RLDE
UDCC0: bit4
0
0
Disable reload
1
Enable reload
UDRC1
UDRC0
UDCC0: bit2
0
Counter clear
1
No impact
UDCC0: bit1-0, bit 2
CGSC
CGE1-0
-
0: Counter clear function
1: Gate function
0
0
Disable edge detection
Disable level detection
0
1
Enable falling edge detection
Enable LOW level detection
1
0
Enable rising edge detection
Enable HIGH level detection
1
1
Disable setting
Disable setting
"Chapter 24 Interrupt Control (Page
UDC0 interrupt
OR
OR
(#128)
UDIE
UDCS0: bit5
0
0
Disable interrupts
OVFF
UDCS0: bit3
1
Enable interrupts
0
No overflow
1
Overflowed
WRITE 0: Flag clear
1
OR
UDFF
UDCS0: bit2
0
No underflow
0
1
Underflowed
0
WRITE 0: Flag clear
CMPF UDCS0: bit4
Com-
0
0
pare
Compare match
1
1
No compare match
WRITE 0: Flag clear
CITE
UDCS0: bit6
0
0
Disable interrupts
1
Enable interrupts
0
1
UCRE
UDCC0:bit5
0
0
Disable counter clear
1
Enable counter clear
No.311)".
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