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Chapter 17 Clock Modulator
3.Application Note
recommended.
1.
define the required PLL frequency based on
performance needs
2.
determine the maximal allowed clock frequency of
the MCU
3.
choose the setting with the highest resolution and
the highest modulation degree, whose maximal
frequency is below the maximal allowed clock
frequency of the MCU.
4.
perform EMI measurements
5.
if the EMI measurements does not fulfill the
requirements, you may either
reduce the modulation degree at the same
frequency resolution
(this may improve the reduction in the upper
frequency band > 100 MHz, but decrease the
reduction of the fundamental < 100 MHz)
or
increase the modulation degree at a lower
frequency resolution
(this may improve the reduction of the fundamental
< 100 MHz, but worsen the reduction in the upper
frequency band > 100 MHz)
6.
repeat item 3) with the new setting and continue
until the best settings is identified
● Recommended settings
The following table lists some example conditions for PLL clock and maximal allowed MCU clock frequency and
the recommended clock modulator setting:
Table 3-1 Some example conditions for PLL clock
F0
maximal allowed
PLL clock
MCU clock
frequency
frequency (refer
to the data
Please refer to the datasheet of each device about modulation parameter settings.
248
resolution
sheet)
e.g. 16 MHz
e.g. 32 MHz
e.g. resolution:7, degree:2, CMPR=0x05F2
(F
= 30.34 MHz)
max
e.g. resolution:7, degree:1, CMPR=0x03F9
or
e.g. resolution:5, degree:3, CMPR=0x0771
clock modulator setting
modulation
degree
F
CMPR
max
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