Fujitsu MB91460 SERIES FR60 User Manual page 621

■ 2-Cycle Transfer (I/O -> SDRAM/FCRAM)
Figure 4.10 - 11 shows an operation timing chart assuming TYP3 to TYP0 set to 1000B, AWR set to 0051H, and
IOWR set to 00H.
Figure 10-11 Timing Chart for Two - cycle Transfer (I/O to SDRAM/FCRAM)
MC LK
A31 to 0
AS
CS n
SRAS
SC AS
WR n(SWE)
CS n
RD
D31 to 0
DACKn
FR30
compatible
mode
DEOPn
DACKn
Basic mode
DEOPn
DREQn
10.9 2-Cycle Transfer (SDRAM/FCRAM -> I/O)
This section describes the operation of two - cycle transfer (SDRAM/FCRAM to I/O device).
■ 2-Cycle Transfer (SDRAM/FCRAM -> I/O)
Figure 1.10 - 12 shows a timing chart for two - cycle transfer (SDRAM/FCRAM to I/O)
I/O
idle
address
Chapter 31 External Bus
10.DMA Access Operation
memory
address
605