Fujitsu MB91460 SERIES FR60 User Manual page 225

(See "Meaning of Bit Attribute Symbols (Page
• Bit7-6: Reserved bits.The read value is always "0".
• Bit5-0: PLL divide-by-N selection
DVN5-DVN0
000000
000001
000010
000011
000100
000101
000110
000111
......
111111
(Note) The register value can not be changed once PLL is selected as clock source (CLKS[1:0]="10").
(Note) It is strongly recommended to disable the PLL (CLKR.PLL1EN=0) while or after changing the
PLLDIVM and PLLDIVN registers and to enable the PLL (CLKR.PLL1EN=1) afterwards.
• PLLDIVG: Address 048Eh (Access: Byte, Halfword, Word)
7 6
- -
0 0
0 0
R0/W0 R0/W0
(See "Meaning of Bit Attribute Symbols (Page
• Bit7-4: Reserved bits.Always write "0" to these bits.
• Bit3-0: PLL auto gear start/end divide-by-G selection
DVG3-DVG0
0000
0001
0010
0011
0100
0101
0110
0111
......
1111
(Note) See chapter
(Note) Even though it is possible to select an odd division ratio (:3, :5, :7, etc.) for the divide-by-G counter it
is not recommended. Always select an even division ratio (:2, :4, :6, etc.).
(Note) The register value can not be changed once PLL is selected as clock source (CLKS[1:0]="10").
5 4 3
- - DVG3
0 0 0
0 0 X
R0/W0 R0/W0 R/W
PLL output divided-by-G start/end frequency (generates Φ: Base clock)
6. Clock Auto Gear Up/Down
No.10)" for details of the attributes.)
Φ: Base clock divide-by-N (feedback to PLL)
Base clock (F
CL-MAIN
) : 2 (division by 2)
Base clock (F
CL-MAIN
) : 3 (division by 3)
Base clock (F
CL-MAIN
) : 4 (division by 4)
Base clock (F
CL-MAIN
) : 5 (division by 5)
Base clock (F
CL-MAIN
) : 6 (division by 6)
Base clock (F
CL-MAIN
) : 7 (division by 7)
Base clock (F
CL-MAIN
) : 8 (division by 8)
Base clock (F
CL-MAIN
.....
) : 64 (division by 64)
Base clock (F
CL-MAIN
2 1
DVG2 DVG1
0 0
X X
R/W R/W
No.10)" for details of the attributes.)
Auto gear disabled (inital value)
) : 2 (division by 2)
Source (F
CL-PLL
) : 3 (division by 3)
Source (F
CL-PLL
) : 4 (division by 4)
Source (F
CL-PLL
) : 5 (division by 5)
Source (F
CL-PLL
) : 6 (division by 6)
Source (F
CL-PLL
) : 7 (division by 7)
Source (F
CL-PLL
) : 8 (division by 8)
Source (F
CL-PLL
.....
) : 16 (division by 16)
Source (F
CL-PLL
for detailed information on how to use this function.
Chapter 14 PLL Interface
) : 1 (no division)
0 bit
DVG0
Initial value (
INIT pin input,
0
watchdog reset
Initial value
X
(Software reset)
R/W Attribute
4.Registers
)
209