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Figure 4-2 Timing Diagram: Initial settings, main clock missing during 'oscillation stabilisation wait time'
PONR
MCLK
SCLK
RC_CLK
OSC_STAB
TO_MCLK
TO_SCLK
MSVE
MSEN
SSVE
SSEN
MCLK_STBY
SCLK_STBY
SRST
EXT_RST
EXT_RST_OUT
MCLK_OUT
SCLK_OUT
MCLK_MISSING
SCLK_MISSING
Chapter 16 Clock Supervisor
4.Operation Modes
227
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