Fujitsu MB91460 SERIES FR60 User Manual page 604

Chapter 31 External Bus
9.SDRAM/FCRAM Interface Operation
Table 9-1 SDRAM/FCRAM Interface to SDRAM/FCRAM Connection Table
SDRAM/ SDRAM/
FCRAM FCRAM pin
interface
pin
SWE (WR) WE
CS0 to CS7 CS
A0 to A9 A0 to A9
A10/AP A10/AP
A11 to A13 A11 to A13
A14 BA0
A15 BA1
D31 to D0 DQ
DQMUU, DQM
DQMUL,
DQMLU,
DQMLL
● Using 8 - bit SDRAM/FCRAM (Big endian)
Total data bus width of 32 bits: Use four SDRAM/FCRAM modules.
Total data bus width of 16 bits: Use two SDRAM/FCRAM modules.
Figure 9-7 shows how to use 64 - Mbit SDRAM (one bank address and 12 row addresses).
588
All chip select areas can be set as SDRAM/FCRAM space.
Addresses do not have to be shifted depending on the bus
width.
A10 for row address output; otherwise AP
Connected to the address used for SDRAM/FCRAM.
BA for 2 bank product
The pin is not used for a two - bank module.
The connection changes depending on the endian method
and data bus width.
For detailed connection, see Section "
Access " .
The connection changes depending on the endian method
and data bus width.
For detailed connection, see Section "
Access " .
Remarks
4. Endian and Bus
4. Endian and Bus