Fujitsu MB91460 SERIES FR60 User Manual page 271

■ Watchdog reset when main clock operating
Although no oscillation stabilization wait is required in this case, the specified wait time is generated
automatically.
5.3 Recovering from Stop Mode via an Interrupt
■ When changing from main PLL operation to stop mode with the main clock oscillation halted
(STCR.OSCD[2:1]="11"):
The main oscillation circuit generates the selected oscillation stabilization time automatically.
Figure 5-3 Recovering from Stop Mode with the Main Clock Halted to
Using the time-base timer to wait
main PLL lock
Example main PLL
startup
(1)
Time-base
counter count
Clear the time-base counter.
(CTBR)
Enable main PLL (PLL1EN)
Enable the time base timer
interrupt request. (PLL1EN)
Time base timer interrupt
request (PLL1EN)
Setting or switching
(2)
the main PLL value
(PLL1S[2:0])
Clock switching (CLKS[1:0])
(1) Enabled interrupt is generated (end stop mode)
(2) The timebase counter is cleared automatically and then starts counting.
(3) Oscillation stabilization wait time (specified value)
(Set the interval time beforehand to provide an adequate oscillation stabilization wait time.)
(4) Interval time for timebase counter
(5) Main PLL operation
Main PLL Operation via an Interrupt
(5) (5)
Provide a sufficient oscillation
stabilization wait time.
13
2
(4)
000h
(3)
"A5" "5A" "
(5)
(7)
(6)
"111"
"00"
Operation of the divided- by-2 main clock
Chapter 18 Timebase Counter
(8) (8)
(9)
(9)
(10)
"10"
Operation of the PLL clock
5.Operation
Time
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