Fujitsu MB91460 SERIES FR60 User Manual page 721

Address
CAN Base + 0x10
CAN Base + 0x12
CAN Base + 0x14
CAN Base + 0x16
CAN Base + 0x18
CAN Base + 0x1A
CAN Base + 0x1C
CAN Base + 0x20
CAN Base + 0x32
CAN Base + 0x22
CAN Base + 0x30
CAN Base + 0x24
CAN Base + 0x36
CAN Base + 0x26
CAN Base + 0x34
■ IFx Command Request Registers (IFxCREQ)
A message transfer is started as soon as the CPU has written the message number to the Command Request
Register. With this write operation the CPU is notified that a transfer is in progress. If a CPU access to the
CAN happens while the transfer is in progress then this access is delayed until the transfer has finished. After
3 to 6 CAN_CLK periods, the transfer between the Interface Register and the Message RAM has completed
and the upcoming CPU access is executed.
IFx Command Request Register high byte
Address : Base + 0x10
IFx Command Request Register low byte
Address : Base + 0x 11
IF1 Register Set
IF1 Command Request
IF1 Command Mask
IF1 Mask 2
IF1 Mask 1
IF1 Arbitration 2
IF1 Arbitration 1
IF1 Message Control
IF1 Data A1
IF1 Data A2
IF1 Data B1
IF1 Data B2
Figure 2-3 IF1 and IF2 Message Interface Register Sets
15
BUSY res
Base + 0x40
H & H
Read/write ⇒ (R/(W)) (R)
(0)
Default value⇒
7
& Base + 0x 41
H H
Read/write ⇒
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
Default value⇒
Address
CAN Base + 0x40
CAN Base + 0x42
CAN Base + 0x44
CAN Base + 0x46
CAN Base + 0x48
CAN Base + 0x4A
CAN Base + 0x4C
CAN Base + 0x50
CAN Base + 0x62
CAN Base + 0x52
CAN Base + 0x60
CAN Base + 0x54
CAN Base + 0x66
CAN Base + 0x56
CAN Base + 0x64
14 13 12 11
res res res
(R) (R) (R)
(0) (0) (0) (0)
6 5 4 3
Message Number
(0) (0) (0) (0)
Chapter 34 CAN Controller
2.Register Description
IF2 Register Set
IF2 Command Request
IF2 Command Mask
IF2 Mask 2
IF2 Mask 1
IF2 Arbitration 2
IF2 Arbitration 1
IF2 Message Control
IF2 Data A1
IF2 Data A2
IF2 Data B1
IF2 Data B2
⇐ Bit no.
10 9 8
res res res
(R) (R) (R)
(0) (0) (0)
⇐ Bit no.
2 1 0
(0) (0) (1)
IFxCREQH
IFxCREQL
705