Fujitsu MB91460 SERIES FR60 User Manual page 650

Chapter 32 USART (LIN / FIFO)
4.USART Registers
4.8 FIFO Control Register (FCR04)
7
R/W R/W R/W R/W
R/W :
R :
:
634
Figure 4-8 Configuration of FIFO control registe
6 5 4 3 2 1
R R/W R/W R/W
Readable and writable
Flag is read only, writing to it
has no effect
Initial value
Initial value
0
0 0 0 0 0 0 0 0
B
bit 0
SVD select Fifo read valid date status for RX / TX
0 Select reading status from RX FIFO
1 Select reading status from TX FIFO
bit 1
ETX
0 Disables TX FIFO
1 Enables TX FIFO
bit 2
ERX
0 Disables RX FIFO
1 Enables RX FIFO
bit 3
not used / always read 0
bit 4
RXL0
0 RX Triggerlevel Bit 0
bit 5
RXL1
0 RX Triggerlevel Bit 1
bit 6
RXL2
0 RX Triggerlevel Bit 2
bit 7
RXL3
0 RX Triggerlevel Bit 3
control TX FIFO (on / off)
control RX FIFO (on / off)
RX Triggerlevel
RX Triggerlevel
RX Triggerlevel
RX Triggerleve