Fujitsu MB91460 SERIES FR60 User Manual page 212

Chapter 13 Clock Control
4.Registers
4.4 CSCFG: Clock Source Configuration Register
This register controls the main clock oscillation in subclock mode
• CSCFG: Address 04AEh (Access: Byte)
7 6
EDSUEN PLLLOCK
0 X
X X
R/W R
(See "Meaning of Bit Attribute Symbols (Page
• bit7: EDSU/MPU Enable
EDSUEN
0
1
• bit6: PLL Lock
PLLLOCK
0
1
• bit5: RC Oscillator Selector
RCSEL
0
1
The selected oscillation frequency is supplied to Clock Control Unit (for Subclock Operation) and Flash Security Unit
(change the oscillation to 2 MHz for faster CRC generation). Hardware Watchdog (RC based Watchdog), Real Time
Clock, Calibration Unit, LCD and Clock Supervisor Module are always supplied with 100 kHz independent of this
setting.
• bit4: Clock Monitor MONCLK inverter
MONCKI
0
1
See chapter "Clock Monitor (Page
• Bit3-0: Clock Source Selection
CSC3-CSC0
196
5 4 3
RCSEL MONCKI CSC3
0 0 0
X X X
R/W R/W R/W
EDSU/MPU is (clock) disabled [Initial value]
EDSU/MPU is (clock) enabled
PLL is in the un-locked state
PLL is in the locked state
RC oscillation is set to 100 kHz [Initial value]
RC oscillation is set to 2 MHz
MONCLK mark level is low [Initial value]
MONCLK mark level is high
No.941)" about information about this function.
--00
--01
--10
--11
-0--
2 1
CSC2 CSC1
0 0
X X
R/W R/W
No.10)" for details of the attributes.)
Function
Function
Function
Function
Function
Real Time Clock is sourced by Main Oscillation
Real Time Clock is sourced by Sub Oscillation
Real Time Clock is sourced by RC Oscillation
Setting prohibited
Subclock Calibration is sourced by Sub Oscillation
0 bit
CSC0
Initial value (INIT pin
0
input, watchdog reset)
Initial value
X
(software reset)
R/W Attribute