Fujitsu MB91460 SERIES FR60 User Manual page 710

Chapter 34 CAN Controller
2.Register Description
Address
+0
Base-addr +
0x40
bit[15:8]
Busy
Reset: 0x00
Base-addr +
0x44
bit[15:8]
MXtd,MDir,Msk[28:24]
Reset: 0xFF
Base-addr +
0x48
bit[15:8]
MsgVal,Xtd,Dir,ID[28:24]
Reset: 0x00
Base-addr +
0x4C
bit[15:8]
see descr. IF2MCTR
Reset: 0x00
Base-addr +
0x50
bit[7:0]
Data[0]
Reset: 0x00
Base-addr +
0x54
bit[7:0]
Data[4]
Reset: 0x00
Base-addr +
0x60
bit[15:8]
Data[3]
Reset: 0x00
Base-addr +
0x64
bit[15:8]
Data[7]
Reset: 0x00
694
+1
IF2 Command Request
bit[7:0]
Mess. No. [5:0]
Reset: 0x01
IF2 Mask 2
bit[7:0]
Msk[23:16]
Reset: 0xFF
IF2 Arbitration 2
bit[7:0]
ID[23:16]
Reset: 0x00
IF2 Message Control
bit[7:0]
see descr. IF2MCTR
Reset: 0x00
IF2 Data A1
bit[15:8]
Data[1]
Reset: 0x00
IF2 Data B1
bit[15:8]
Data[5]
Reset: 0x00
IF2 Data A2
bit[7:0]
Data[2]
Reset: 0x00
IF2 Data B2
bit[7:0]
Data[6]
Reset: 0x00
Register
+2
IF2 Command Mask
bit[15:8]
reserved
Reset: 0x00
IF2 Mask 1
bit[15:8]
Msk[15:8]
Reset: 0xFF
IF2 Arbitration 1
bit[15:8]
ID[15:8]
Reset: 0x00
Reserved
bit[7:0]
reserved
Reset: 0x00
IF2 Data A2
bit[7:0]
Data[2]
Reset: 0x00
IF2 Data B2
bit[7:0]
Data[6]
Reset: 0x00
IF2 Data A1
bit[15:8]
Data[1]
Reset: 0x00
IF2 Data B1
bit[15:8]
Data[5]
Reset: 0x00
+3
bit[7:0]
see descr. IF2CMSK
Reset: 0x00
bit[7:0]
Msk[7:0]
Reset: 0xFF
bit[7:0]
ID[7:0]
Reset: 0x00
bit[15:8]
reserved
Reset: 0x00
Big Endian byte
ordering.
bit[15:8]
Data[3]
Reset: 0x00
Big Endian byte
ordering.
bit[15:8]
Data[7]
Reset: 0x00
Little Endian byte
ordering.
bit[7:0]
Data[0]
Reset: 0x00
Little Endian byte
ordering.
bit[7:0]
Data[4]
Reset: 0x00
Note