Fujitsu MB91460 SERIES FR60 User Manual page 709

Address
+0
Base-addr +
0x10
bit[15:8]
Busy
Reset: 0x00
Base-addr +
0x14
bit[15:8]
MXtd,MDir,Msk[28:24]
Reset: 0xFF
Base-addr +
0x18
bit[15:8]
MsgVal,Xtd,Dir,ID[28:24]
Reset: 0x00
Base-addr +
0x1C
bit[15:8]
see descr. IF1MCTR
Reset: 0x00
Base-addr +
0x20
bit[7:0]
Data[0]
Reset: 0x00
Base-addr +
0x24
bit[7:0]
Data[4]
Reset: 0x00
Base-addr +
0x30
bit[15:8]
Data[3]
Reset: 0x00
Base-addr +
0x34
bit[15:8]
Data[7]
Reset: 0x00
+1
IF1 Command Request
bit[7:0]
Mess. No. [5:0]
Reset: 0x01
IF1 Mask 2
bit[7:0]
Msk[23:16]
Reset: 0xFF
IF1 Arbitration 2
bit[7:0]
ID[23:16]
Reset: 0x00
IF1 Message Control
bit[7:0]
see descr. IF1MCTR
Reset: 0x00
IF1 Data A1
bit[15:8]
Data[1]
Reset: 0x00
IF1 Data B1
bit[15:8]
Data[5]
Reset: 0x00
IF1 Data A2
bit[7:0]
Data[2]
Reset: 0x00
IF1 Data B2
bit[7:0]
Data[6]
Reset: 0x00
Register
+2
IF1 Command Mask
bit[15:8]
reserved
Reset: 0x00
IF1 Mask 1
bit[15:8]
Msk[15:8]
Reset: 0xFF
IF1 Arbitration 1
bit[15:8]
ID[15:8]
Reset: 0x00
Reserved
bit[15:8]
reserved
Reset: 0x00
IF1 Data A2
bit[7:0]
Data[2]
Reset: 0x00
IF1 Data B2
bit[7:0]
Data[6]
Reset: 0x00
IF1 Data A1
bit[15:8]
Data[1]
Reset: 0x00
IF1 Data B1
bit[15:8]
Data[5]
Reset: 0x00
Chapter 34 CAN Controller
2.Register Description
+3
bit[7:0]
see descr. IF1CMSK
Reset: 0x00
bit[7:0]
Msk[7:0]
Reset: 0xFF
bit[7:0]
ID[7:0]
Reset: 0x00
bit[7:0]
reserved
Reset: 0x00
Big Endian byte
ordering.
bit[15:8]
Data[3]
Reset: 0x00
Big Endian byte
ordering.
bit[15:8]
Data[7]
Reset: 0x00
Little Endian byte
ordering.
bit[7:0]
Data[0]
Reset: 0x00
Little Endian byte
ordering.
bit[7:0]
Data[4]
Reset: 0x00
Note
693