Fujitsu MB91460 SERIES FR60 User Manual page 537

AWR5H
15
0000 066A W15
H
AWR5L 7
0000 066B W07
H
AWR6H 31
0000 066C W15
H
23
AWR6L
0000 066D W07
H
AWR7H 15
0000 066E W15
H
7
AWR7L
0000 066F W07
H
The function of each bit changes according to the access type (TYP(3-0) bits) setting of the ACR0-7 registers,. A
chip select area determined by either of the following settings becomes the area for normal access or a address/
data multiplex access operation.
TYP3 TYP2
0 0
0 1
The following lists the functions of each AWR0-7 bit for a normal access or address/data multiplex access area.
Since the initial values of registers other than AWR0 are undefined, set them to their initial values before enabling
each area with the CSER register.
The following explains the functions of the bits in the area wait registers (AWR0-7).
14 13 12 11
W14 W13 W12 W11
6 5 4 3
W06 W05 W04 W03
30 29 28 27
W14 W13 W12 W11
22 21 20 19
W06 W05 W04 W03
14 13 12 11
W14 W13 W12 W11
6 5 4 3
W06 W05 W04 W03
TYP1 TYP0
Normal access (asynchronous SRAM, I/O,
x x
and single/page/burst-ROM/FLASH)
Address data multiplex access (8/16-bit bus
x x
width only)
10 9 8
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W10 W09 W08
2 1 0
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W02 W01 W00
26 25 24
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W10 W09 W08
18 17 16
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W02 W01 W00
10 9 8
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W10 W09 W08
2 1 0
W02 W01 W00
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Access type
Chapter 31 External Bus
2.External Bus Interface Registers
Initial value
INIT RST
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b b
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b b
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b b
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b b
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b b
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b b
Access
W/R
W/R
W/R
W/R
W/R
W/R
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