Fujitsu MB91460 SERIES FR60 User Manual page 282

Chapter 19 Timebase Timer
4.Register
• Bit1: Enabling the synchronous reset operation
SYNCR
0
1
• Ordinary operation reset: Immediately resets the operation initialization when the operation initialization
reset (RST) request is generated.
Synchronous reset: Resets the operation initialization after all accesses to the bus have stopped.
• Bit0: Synchronous standby operation enable
SYNCS
0
1 Synchronous standby operation enable (Be sure to set before making the transition to standby)
4.2 CTBR: Timebase Counter Clear Register
This register is used to initialize the timebase counter.
• CTBR: Address 0483h (Access: Byte)
7 6
D7 D6
X X
RX/W RX/W
(Refer to "Meaning of Bit Attribute Symbols (Page
• Continuously writing
immediately after writing
There is no time restrictions between
5A , you should write
" "
H
• The read value is indefinite.
• Clearing the timebase counter using the timebase counter clear register temporarily modifies the relevant
items shown below.
• Oscillation stability wait interval
• Watchdog timer period
• Timebase timer period
266
Synchronous reset operation enable
Ordinary reset operation (In this product, any setting is prohibited)
5 4 3
D5 D4 D3
X X X
RX/W RX/W RX/W
A5 , 5A in the timebase counter clear register clears the timebase counter
" " " "
H H
5A . (All bits are
" "
H
A5
"
H
A5 again. If not, the timebase counter cannot be cleared even if
" "
H
Operation
Ordinary reset operation
Operation
2 1
D2 D1
X X
RX/W RX/W
No.10)" for the attributes)
0 )
" "
and 5A , but if A5
" " " "
H H
0 bit
D0
X Initial value
RX/W Attribute
is written followed by the one other than
"
5A is written.
" "
H