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Figure 4-6 Configuration of the Extended Communication Control Register (ECCR04)
7
6
5
4
R/W
W R/W R/W
R/W
R/W
:
Readable and writable
R
:
Flag is read only
W
:
Flag is write only
X
:
Indeterminate
:
Initial value
3
2
1
0
Initial value
0 0 0 0 0 0 X X
R/W
R
R
bit0
TBI *
0
1
bit1
RBI *
0
1
bit2
BIE *
0
1
bit3
SSM
0
1
bit4
SCDE
0
1
bit5
MS
0
1
bit6
LBR
0
1
bit7
INV
0
1
* not useable in mode 2
Chapter 32 USART (LIN / FIFO)
B
Transmission bus idle
Transmission is ongoing
no transmission activity
Reception bus idle
Reception is ongoing
no reception activity
Bus idle interrupt enable
disable Bus idle interrupt
enable Bus idle interrupt
Synchronous start/stop bits in mode 2
No start/stop bits in synchronous mode 2
Enable start/stop bits in synchronous mode 2
Serial Clock Delay enable in mode 2
disable clock delay
enable clock delay
Master / Slave function in mode 2
Master mode (generating serial clock)
Slave mode (receiving external serial clock)
Set LIN break
write
read
ignored
always read 0
Generate LIN break
Invert Serial Data
Serial data is not inverted (NRZ format)
Serial data is inverted (RZ format)
4.USART Registers
631
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