Fujitsu MB91460 SERIES FR60 User Manual page 187

Important remark: To maintain data consistency it is strongly recommended to disable the instruction cache while
writing to the FLASH memory and to flush the instruction cache (FLUSH=1) after completing the write procedure to
the FLASH memory.
Important remark: It is not allowed to switch between the 16 bit, the 32 bit and the 64 bit mode while reading instruc-
tions or data from the FLASH memory.
• BIT[24]: LPM - Low Power Mode
0 Low power mode off (default)
1 Low power mode enabled
This bit is cleared after reset. The low power mode is switched off by default.
If LPM=0, CEX is permanently asserted to '0' (active). This enables fastest possible FLASH access timing.
Setting this bit to '1' enables the low power mode. CEX is asserted low only in case of FLASH access. In between
the FLASH macro is in stand-by mode.
Remark: On the MB91460 series with embedded FLASH memories it is not necessary to use this setting
since the FLASH memory supports an "automatic sleep mode" which puts the FLASH automatically in a
low power consumption state when not accessed.
FLASH Memory Control Register (FMCR)
The FMCR register is not available on the evaluation device MB91V460.
• BIT[19]: LOCK - ALEH auto-update lock
0 ALEH setting auto update is enabled (default)
1 ALEH setting auto update is disabled
FLASH memories embedded on the MB91460 series require a certain timing between ATDIN falling edge and EQIN
rising edge. This timing is named tALEH and has usually the same length as the ATDIN duration.
By writing the setting of ATDIN length to the FMWT.ATD[2:0] bits, the FMWT2.ALEH[2:0] bits will be updated auto-
matically to the same setting. To avoid this automatic update it is possible to set the ALEH LOCK bit.
It is also possible to apply a different setting to the FMWT2.ALEH[2:0] bits by writing first to the FMWT.ATD[2:0] bits
and second to the FMWT2.ALEH[2:0] bits.
• BIT[18]: PHASE - ATDIN/EQIN clock phase
0 ATDIN/EQIN generation is in phase with the core clock (default)
1 ATDIN/EQIN generation is inverted to the core clock
At lower core clock frequencies it can be beneficial to change the ATDIN/EQIN generation to inverted core clock to
save a waitcycle compared to the generation of these signals in phase with the core clock.
It is recommended to always refer to the setting requirements of ATDIN, EQIN and waitcycles for each product
which are provided by Fujitsu (see the related datasheets).
(PHASE setting is not available on MB91460 series)
Chapter 11 Memory Controller
8.Explanations of Registers
171