Fujitsu MB91460 SERIES FR60 User Manual page 805

7. Q & A
7.1 What is the reload value setting (rewriting) procedure?
The reload value is set by the 16 bit reload registers TMRLR0-TMRLR7.
The equation for the values to be set is as follows.
• Formula
TMRLR register value = {reload interval/count clock}-1
• Allowed Range
TMRLR register value = 0~FFFh (65535)
7.2 What are the kinds of count clocks and how are they selected?
The count clock is chosen from the 4 types in the table below.
Selection is done via the count clock selection bit.
Table 7-1 TMCSR.CSL[2:0]
Counter clock selection bit
Count
Clock
CSL2
CLKP/2
CLKP/8
CLKP/32
External event
CLKP/64
CLKP/128
Disabled *
(*: See "8. Caution (Page
7.3 How to I enable/disable the reload timer count operation?
Use the timer count enable bit (TMCSR.CNTE).
Control Details
To stop the reload timer
To enable the reload timer's count operation
Cannot be reopened from the stopped state. Enable before activation or simultaneous with activation.
7.4 How do I set the reload timer mode (reload/one-shot)?
Use mode selection bit (TMCSR.RELD).
Operation Mode
To set to one-shot mode
To set to reload
7.5 How do I reverse the output level?
The settings for the output level are detailed in the following table.
The setting is done via timer output level bit (TMCSR.OUTL).
CSL1 CSL0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 1
1 1 0
1 0 0
1 1 1
No.794)".)
Output level
Count clock example
When CLKP= When CLKP=
32MHz 16MHz
62.5ns 125ns
250ns 500ns
1.0µs 2.0µs
Pulse width: 2/CLKP min
2.0µs 4.0µs
4.0µs 8.0µs
RLT operation permission bit (CNTE)
Mode selection bit (RELD)
Chapter 38 Reload Timer
When CLKP= 8MHz
250ns
1.0µs
4.0µs
8.0µs
16.0µs
-----
-----
Set to "0"
Set to "1"
Set to "0"
Set to "1"
Timer output level bit (OUTL)
7.Q & A
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