Fujitsu MB91460 SERIES FR60 User Manual page 976

Chapter 49 Real-Time Clock
7.Q&A
7.8 What are interrupt-related registers?
RTC interrupt vector and level settings.
The following table shows the relationship between interrupt levels and vectors.
For details on interrupt levels and vectors, refer to
Interrupt vectors (Default)
#132 (0FFDECh)
The interrupt request flags (INT0,INT1,INT2,INT3 and INT4) are not automatically cleared, so the software
must clear them by writing
7.9 What interrupts are available and how are they selected?
There are four interrupt causes:
Interrupt cause
On counting seconds
On counting minutes
On counting hours
On counting days
On counting half-seconds
An interrupt request is made by ORing these four interrupt causes. Each cause can be selected with the
corresponding interrupt request enable bit.
7.10 How do I enable interrupts?
Use the interrupt request enable bits (WTCR.INTE0, WTCR.INTE1, WTCR.INTE2, WTCR.INTE3 and
WTCER.INTE4).
To disable interrupts
To enable interrupts
To clear interrupt requests,
Use the interrupt request bits (WTCR.INT0, WTCR.INT1, WTCR.INT2, WTCR.INT3 and WTCER.INT4).
To clear interrupt requests
960
0" to these flags before control is returned from interrupt processing.
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Interrupt request enable bits (INTE0, INTE1, INTE2, INTE3 and INTE4)
Interrupt request bits (INT0, INT1, INT2, INT3 and INT4)
"Chapter 24 Interrupt Control (Page No.311)
Interrupt level set bit (ICR[4.0])
Interrupt level register ICR58 (047Ah)
Interrupt request bit
INT0
INT1
INT2
INT3
INT4
Setting Procedure
Set the bit to "0".
Set the bit to "1".
Setting Procedure
Write "0".
".
Interrupt request enable
bits
INTE0
INTE1
INTE2
INTE3
INTE4