Fujitsu MB91460 SERIES FR60 User Manual page 711

Address
+0
Base-addr + Transmission Request Register 2
0x80
bit[15:8]
TxRqst[32-25]
Reset: 0x00
Base-addr +
0x84
Base-addr +
0x90
bit[15:8]
NewDat[32-25]
Reset: 0x00
Base-addr +
0x94
Base-addr +
0xA0
bit[15:8]
IntPnd[32-25]
Reset: 0x00
Base-addr +
0xA4
Base-addr +
0xB0
bit[15:8]
MsgVal[32-25]
Reset: 0x00
Base-addr +
0xB4
Address
+0
0x04C0
CANPRE
bit[3:0]
CANPRE[3:0]
Reset: 0x00
2.2 Hardware Reset Description
After hardware reset, the registers of the CAN hold the values described in
+1
bit[7:0]
TxRqst[24-17]
Reset: 0x00
Reserved ( >32..128 Message buffer)
New Data 2
bit[7:0]
NewDat[24-17]
Reset: 0x00
Reserved ( >32..128 Message buffer)
Interrupt Pending 2
bit[7:0]
IntPnd[24-17]
Reset: 0x00
Reserved ( >32..128 Message buffer)
Message Valid 2
bit[7:0]
MsgVal[24-17]
Reset: 0x00
Reserved ( >32..128 Message buffer)
Figure 2-1 CAN Register Summary
+1
CANCKD
bit[5:0]
CANCKD[5:0]
Reset: 0x00
Figure 2-2 CAN Prescaler Register Summary
Register
+2
Transmission Request Register 1
bit[15:8]
TxRqst[16-9]
Reset: 0x00
New Data 1
bit[15:8]
NewDat[16-9]
Reset: 0x00
Interrupt Pending 1
bit[15:8]
IntPnd[16-9]
Reset: 0x00
Message Valid 1
bit[15:8]
MsgVal[16-9]
Reset: 0x00
Register
+2
-
-
-
-
Chapter 34 CAN Controller
2.Register Description
+3
Transmission
Request Register is
bit[7:0]
read only.
TxRqst[8-1]
Reset: 0x00
New Data is read
only.
bit[7:0]
NewDat[8-1]
Reset: 0x00
Interrupt Pending is
read only.
bit[7:0]
IntPnd[8-1]
Reset: 0x00
Message Valid is
read only.
bit[7:0]
MsgVal[8-1]
Reset: 0x00
+3
- CAN Prescaler
-
-
-
Figure 2-1.
Note
Note
695