Fujitsu MB91460 SERIES FR60 User Manual page 687

This bit is not valid when receiving address bytes in slave mode - if the interface detects its 7 or 10 bit slave
address, it will acknowledge if the corresponding enable bit (ENTB in ITMK0 or ENSB in ISMK0) is set.
Write access to this bit should occur during an interrupt (INT='1') or if the bus is idle (BB='0' in the IBSR0
register) write access to this bit is only possible if the interface is enabled (EN='1' in ICCR0) and if there is no
bus error (BER='0' in IBCR0).
[bit 10] GCAA (General Call Address Acknowledge)
This bit enables acknowledge generation when a general call address is received. It can only be changed by
the user.
0
1
Write access to this bit should occur during an interrupt (INT='1') or if the bus is idle (BB='0' in IBSR0 register)
write access to this bit is only possible if the interface is enabled (EN='1' in ICCR0) and if there is no bus error
(BER='0' in IBCR0).
[bit 9] INTE (INTerrupt Enable)
This bit enables the MCU interrupt generation. It can only be changed by the user.
0
1
Setting this bit to '1' enables MCU interrupt generation when the INT bit is set to '1' (by the hardware).
[bit 8]: INT (INTerrupt)
This bit is the transfer end interrupt request flag. It is changed by the hardware and can be cleared by the
user. It always reads '1' in a Read-Modify-Write access.
(Write access)
0
1
(Read access)
0
1
The interface will not acknowledge on general call address byte reception.
The interface will acknowledge on general call address byte reception.
Interrupt disabled.
Interrupt enabled.
Clear transfer end interrupt request flag.
No effect.
Transfer not ended or not involved in current transfer or bus is idle.
Set at the end of a 1-byte data transfer or reception including the acknowledge bit
under the following conditions:
• Device is bus master.
• Device is addressed as slave.
• General call address received.
• Arbitration loss occurred.
Set at the end of an address data reception (after first byte if seven bit address
received, after second byte if ten bit address received) including the acknowledge
bit if the device is addressed as slave.
Chapter 33 I2C Controller
2.I2C Interface Registers
671