Table of Contents
Advertisement
Chapter 34 CAN Controller
2.Register Description
1
This message object is the source of an interrupt.
These registers hold the IntPnd bits of the 32 Message Objects. By reading out the IntPnd bits, the CPU can
check for which Message Object an interrupt is pending. The IntPnd bit of a specific Message Object can be
set/reset by the CPU via the IFx Message Interface Registers or by the Message Handler after reception or
after a successful transmission of a frame. This will also affect the value of IntId in the Interrupt Register.
If more than 32 message buffers are implemented, the following table gives an overview about the additional
flags:
Table 2-3 Additional flags when more than 32 message buffers exist
INTPND 4 & 3
IntPnd 64-33 (address 0xA4)
INTPND 6 & 5
IntPnd 96-65 (address 0xA8)
INTPND 8 & 7
IntPd 128-97 (address 0xAC)
■ Message Valid Registers (MSGVAL)
Message Valid Register 2 high byte
Address : Base + 0xB0
Message Valid Register 2 low byte
Address : Base + 0x B1
Message Valid Register 1 high byte
Address : Base + 0xB2
Message Valid Register 1 low byte
Address : Base + 0x B3
718
15
H
Read/write ⇒
(R)
(0)
Default value⇒
7
H
Read/write ⇒
(R)
(0)
Default value⇒
15
H
Read/write ⇒
(R)
(0)
Default value⇒
7
H
Read/write ⇒
(R)
(0)
Default value⇒
addr+0
addr+1
IntPnd64-57
IntPnd56-49
IntPnd96-89
IntPnd88-81
IntPnd128-
IntPnd120-
121
113
14
13
12
11
MsgVal32-25
(R)
(R)
(R)
(R)
(0)
(0)
(0)
(0)
6
5
4
3
MsgVal24-17
(R)
(R)
(R)
(R)
(0)
(0)
(0)
(0)
14
13
12
11
MsgVal16-9
(R)
(R)
(R)
(R)
(0)
(0)
(0)
(0)
6
5
4
3
MsgVal8-1
(R)
(R)
(R)
(R)
(0)
(0)
(0)
(0)
addr+2
IntPnd48-41
IntPnd80-73
IntPnd112-
105
⇐ Bit no.
10
9
8
(R)
(R)
(R)
(0)
(0)
(0)
⇐ Bit no.
2
1
0
(R)
(R)
(R)
(0)
(0)
(0)
⇐ Bit no.
10
9
8
(R)
(R)
(R)
(0)
(0)
(0)
⇐ Bit no.
2
1
0
(R)
(R)
(R)
(0)
(0)
(0)
addr+3
IntPnd40-33
IntPnd72-65
IntPnd104-
97
MSGVAL2H
MSGVAL2L
MSGVAL1H
MSGVAL1L
Advertisement
Table of Contents
