Fujitsu MB91460 SERIES FR60 User Manual page 714

Chapter 34 CAN Controller
2.Register Description
recovery sequence, the Error Management Counters will be reset.
(Note) During the waiting time after the resetting of Init, each time a sequence of 11 recessive bits has
been monitored, a Bit0Error code is written to the Status Register, enabling the CPU to readily
check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the
proceeding of the busoff recovery sequence.
■ Status Register (STATR)
Status Register high byte
Address : Base + 0x02
Status Register low byte
Address : Base + 0x 03
698
15
res
H
Read/write ⇒
(R)
(0)
Default value⇒
7
BOff EWarnEPassRxOK TxOK
H
Read/write ⇒
(R)
(0)
Default value⇒
14 13 12 11
res res res res
(R) (R) (R) (R)
(0) (0) (0) (0)
6 5 4 3
(R) (R) (R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0) (0) (0)
⇐ Bit no.
10 9 8
res res res
(R) (R) (R)
(0) (0) (0)
⇐ Bit no.
2 1 0
LEC
(0) (0) (0)
STATRH
STATRL