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F
: Frequency of Peripheral clock (CLKP)
CLKP
This setting is enabled only in the timer mode, in which only countdown is performed.
• bit11,10: Select count mode
CMS1
CMS0
0
0
0
1
1
0
1
1
• bit9,8: Select count clock edge
CES1
CES0
0
0
0
1
1
0
1
1
This bit is used in the up/down count mode (CMS1,CMS0= "01") to select the edge, to be detected, of an
AIN and BIN pin signal. This setting is disabled in modes other than the up/down count.
• bit7: Reserved.
Be sure to write "0". The read value is the value written.
• bit6: Counter write
CTUT
0
No impact on operation
1
Transfer data from the RCR register to UDCR.
During count operation (CSR.CSTR="1"), the counter write bit must not be set to "1".
• bit5: Enable compare-match clear
UCRE
0
Disable counter clear due to compare-match.
1
Enable counter clear due to compare-match.
This setting does not affect clear operations other than compare-match, such as ZIN pin clear.
• bit4: Enable reload
RLDE
0
Disable reload function.
1
Enable reload function.
If the reload enable bit is set to "1", the reload/compare value (RCR) is transferred to Up/Down Counter
(UDCR) when Up/Down Counter is underflowed.
• bit3: Clear UDCR
UDCLR
0
Set (Clear) Up/Down Counter (UDCR) to "0000H".
1
No impact on operation
• bit2: Select counter clear/gate
CGSC
0
Counter clear function
1
Gate function
Timer mode (Countdown)
Up/down count mode
Phase difference count mode (Multiply by 2)
Phase difference count mode (Multiply by 4)
Disable edge detection.
Detect a falling edge.
Detect a rising edge.
Detect both rising and falling edges.
Compare-match counter clear
Count mode
Edge selection
Data transfer
Reload function
Counter clear
ZIN pin function
Chapter 41 Up/Down Counter
4.Register
841
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