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4.2 DIV0R: Clock Division Setting Register 0
Sets the division ratio for the clocks used for internal device operation.
DIVR0: Address 0486h (Access: Byte, Half-word)
7
6
B3
B2
0
0
X
X
R/W
R/W
(See
"Meaning of Bit Attribute Symbols (Page
• Sets up the clock for the CPU and internal buses (CLKB), and the clock for the peripheral circuits and
peripheral bus (CLKP).
• Bit7-4: CLKB division selection
B3-B0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
• Do not change the division ratio with B3-B0 if current CLKB frequency is equal or above 80MHz !
• Sets the clock division ratio for the clock used by the CPU, internal memory, and internal buses (CLKB).
The 16 options listed in the table are available.
• Do not set a division ratio that exceeds the maximum operating frequency of the device.
• Bit3-0: CLKP division selection
P3-P0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
5
4
3
B1
B0
P3
0
0
0
X
X
X
R/W
R/W
R/W
2
1
P2
P1
0
1
X
X
R/W
R/W
No.10)" for details of the attributes.)
CPU clock (CLKB) division ratio
Φ/1 (initial value)
Φ/2
Φ/3
Φ/4
Φ/5
Φ/6
Φ/7
Φ/8
Φ/9
Φ/10
Φ/11
Φ/12
Φ/13
Φ/14
Φ/15
Φ/16
Peripheral clock (CLKP) division ratio
Φ/1
Φ/2
Φ/3
Φ/4 (initial value)
Φ/5
Φ/6
Φ/7
Φ/8
Φ/9
Φ/10
Chapter 13 Clock Control
0
bit
P0
Initial value (
INIT pin input,
1
watchdog reset
Initial value
X
(software reset)
R/W
Attribute
4.Registers
)
193
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