Fujitsu MB91460 SERIES FR60 User Manual page 442

Chapter 29 MPU / EDSU
4.Registers
The input value and the point value is masked if the mask function is enabled by EM0. On a compare match a break
exception will be executed. CTC and MPE control the selection of the input value and the type of the break excep-
tion.
BIT[4]: EP0 - Enable break Point 0 register
0 Break point 0 register is disabled (default)
1 Break point 0 register is enabled
If EP0 is enabled then the input value of CMP0 will be compared with the point 0 register content (BAD index =
0+group offset, BAD0 for group 0 channel 0, BAD4 for group 1 channel 0, ...).
The input value and the point value is masked if the mask function is enabled by EM0. On a compare match a break
exception will be executed. CTC and MPE control the selection of the input value and the type of the break excep-
tion.
EP0 controls in addition to enabling and allocating point 0 the selection of the mask register. Point 0 is also the de-
fault place for storing the CMP0 mask value. But, if point 0 is enabled, the mask could not be stored there and the
mask input of CMP0 switches to point 2 (to the opposite comparator).
If memory protection is enabled (MPE=1) in conjunction with the combination bit set (COMB=1), the address range
is defined by point 3 and point 2 and is valid for both comparators COMB1 and COMB0. So the points 1 and 0 are
not required for the range definition of CMP0, independent from the point enable EP0 and EP1, which normally are
set in this case. Thus point 0 could be used for storing the mask value for both comparators CMP1 and CMP0 and
the exception described in the paragraph above did not apply for this case.
Enable Mask And Range Register
BIT[3]: EM1 - Enable Mask for CMP1
0 Mask function for CMP1 is disabled (default)
1 Mask function for CMP1 is enabled
If EM1 is enabled the comparator CMP1 matches only these bit positions, which are set to '0' and are not masked
by the mask register. All inputs for points and the compare value itself are OR-combined with the value from the
mask register. The compare operations point match or range detection are derived based on these OR-masked val-
ues.
The selection of the appropriate BADx register (point 2 or 0) for the mask value depends on EP2 and ER1. If at least
one of both bits are enabled, the mask usage switches to point 0 due to the allocation of point 2. Otherwise the
default mask stored in point 2 applies for CMP1.
BIT[2]: EM0 - Enable Mask for CMP0
0 Mask function for CMP0 is disabled (default)
1 Mask function for CMP0 is enabled
If EM0 is enabled the comparator CMP0 matches only these bit positions, which are set to '0' and are not masked
by the mask register. All inputs for points and the compare value itself are OR-combined with the value from the
mask register. The compare operations point match or range detection are derived based on these OR-masked val-
ues.
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