Fujitsu MB91460 SERIES FR60 User Manual page 532

Chapter 31 External Bus
2.External Bus Interface Registers
Table 2-1 Area Size Settings
ASZ3 ASZ2
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
ASZ3-0 are used to set the size of each area by modifying the number of bits for address comparison to a value
different from ASR. Thus, an ASR contains bits that are not compared. Bits ASZ3-0 of ACR0 are initialized to
1111 (0F ) by RST. Despite this setting, however, the CS0 area just after RST is executed is specially set from
B H
00000000 to FFFFFFFF
H
and an appropriate size is set as indicated in
[Bits 11-10] DBW1-0 (Data Bus Width 1-0)
These bits set the data bus width of each chip select area as indicated in
Width of Each Chip Select Area":
Table 2-2 Setting of the Data Bus Width of Each Chip Select Area
DBW1 DBW0
0
0
1
1
The same values as those of the WTH bits of the mode vector are written automatically to bits DBW1-0 of ACR0
during the reset sequence.
[Bits 9-8] BST1-0 (Burst Size 1-0)
These bits set the maximum burst length of each chip select area as indicated in
Maximum Burst Length of Each Chip Select".
Table 2-3 Setting of the Maximum Burst Length of Each Chip Select
BST1 BST0
0
0
516
ASZ1 ASZ0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
(setting of entire area). The entire-area setting is reset after the first write to ACR0
H
Table 2-1
0 8 bits (byte access)
1 16 bits (halfword access)
0 32 bits (word access)
1 Reserved Setting disabled
0 1 (single access)
1 2 bursts (address boundary: 1 bit)
Size of each chip select area
8 MB (00800000 byte, ASR A[31:23] bits are valid)
H
16 MB (01000000 byte, ASR A[31:24] bits are valid)
H
32 MB (02000000 byte, ASR A[31:25] bits are valid)
H
64 MB (04000000 byte, ASR A[31:26] bits are valid)
H
128 MB (08000000 byte, ASR A[31:27] bits are valid)
H
256 MB (10000000 byte, ASR A[31:28] bits are valid)
H
512 MB (20000000 byte, ASR A[31:29] bits are valid)
H
1024 MB (40000000 byte, ASR A[31:30] bits are valid)
H
2048 MB (80000000 byte, ASR A[31] bit is valid)
H
"Area Size Settings".
Data bus width
Maximum burst length
Table 2-2 "Setting of the Data Bus
Table 2-3 "Setting of the