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Figure 5-11 Timing Chart for DMA Fly-By Transfer (Memory -> I/O)
Basic cycle
MCLK
A[31:0]
AS
CSn
RD
D[31:0]
IOWR
•
Setting 1 for the HLD bit of the IOWR0-3 registers enables the I/O read cycle to be extended by one cycle.
•
Setting the WR1,0 bits of the IOWR0-3 registers enables 0-3 write recovery cycles to be inserted.
•
If the write recovery cycle is set to 1 or more, a write recovery cycle is always inserted after write access.
•
Setting bits IW3-0 of the IOWR0-3 registers enables 0-15 wait cycles to be inserted.
•
If wait is also set on the memory side (AWR15-12 is not 0), the larger value is used as the wait cycle after
comparison with the I/O wait (IW3-0 bits).
I/O wait
I/O hold
I/O idle
cycle *1
wait *2
cycle
5.Operation of the Ordinary bus interface
I/O wait
cycle *1
Basic cycle
Chapter 31 External Bus
I/O hold
wait *2
573
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