Fujitsu MB91460 SERIES FR60 User Manual page 441

32-bit microcontroller
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OBS1
OBS0
1
1
The operand break size register OBS configures the datasize and the operand break type register OBT configures
the access type if the channel is configured to operand address break or data value break detection.
Setting to 'all' in datasize will cause detection of byte, halfword and word data sizes. Setting to 'all' in access type
will cause detection of Read, Read-Modify-Write and Write access types.
Enable Break Point Register
BIT[7]: EP3 - Enable break Point 3 register
0
Break point 3 register is disabled (default)
1
Break point 3 register is enabled
If EP3 is enabled then the input value of CMP1 will be compared with the point 3 register content (BAD index =
3+group offset, BAD3 for group 0 channel 3, BAD7 for group 1 channel 3, ...).
The input value and the point value is masked if the mask function is enabled by EM1. On a compare match a break
exception will be executed. CTC and MPE control the selection of the input value and the type of the break excep-
tion.
BIT[6]: EP2 - Enable break Point 2 register
0
Break point 2 register is disabled (default)
1
Break point 2 register is enabled
If EP2 is enabled then the input value of CMP1 will be compared with the point 2 register content (BAD index =
2+group offset, BAD2 for group 0 channel 2, BAD6 for group 1 channel 2, ...).
The input value and the point value is masked if the mask function is enabled by EM1. On a compare match a break
exception will be executed. CTC and MPE control the selection of the input value and the type of the break excep-
tion.
EP2 controls in addition to enabling and allocating point 2 the selection of the mask register. Point 2 is also the de-
fault place for storing the CMP1 mask value. But, if point 2 is enabled, the mask could not be stored there and the
mask input of CMP1 switches to point 0 (to the opposite comparator).
BIT[5]: EP1 - Enable break Point 1 register
0
Break point 1 register is disabled (default)
1
Break point 1 register is enabled
If EP1 is enabled then the input value of CMP0 will be compared with the point 1 register content (BAD index =
1+group offset, BAD1 for group 0 channel 1, BAD5 for group 1 channel 1, ...).
Datasize
All (Byte, Hword, Word)
Access type
OBT1
OBT0
1
1
All (Read, RMW, Write)
Chapter 29 MPU / EDSU
4.Registers
425

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