Fujitsu MB91460 SERIES FR60 User Manual page 689

2.2 Bus Status Register (IBSR0)
The bus status register (IBSR0) has the following functions:
• Bus busy detection
• Repeated start condition detection
• Arbitration loss detection
• Acknowledge detection
• Data transfer direction indication
• Addressing as slave detection
• General call address detection
• Address data transfer detection
This register is read-only, all bits are controlled by the hardware. All bits are cleared if the interface is not
enabled (EN='0' in ICCR0).
Bus status register
Address : 0000D1
[bit 7] BB (Bus Busy)
This bit indicates the status of the I
0
1
This bit is set to '1' if a start condition is detected. It is reset upon a stop condition.
[bit 6] RSC (Repeated Start Condition)
This bit indicates detection of a repeated start condition.
0
1
This bit is cleared at the end of an address data transfer (ADT='0') or detection of a stop condition.
[bit 5] AL (Arbitration Loss)
This bit indicates an arbitration loss.
0
1
This bit is cleared by writing '0' to the INT bit or by writing '1' to the MSS bit in the IBCR0 register.
An arbitration loss occurs if:
• the data sent does not match the data read on the SDA line at the rising SCL edge
7
BB
H
Read/write ⇒
(R)
(0)
Default value⇒
2
C bus.
Stop condition detected (bus idle).
Start condition detected (bus in use).
Repeated start condition not detected.
Bus in use, repeated start condition detected.
No arbitration loss detected.
Arbitration loss occurred during master sending.
6 5 4 3
RSC AL LRB TRX
(R) (R) (R) (R)
(0) (0) (0) (0)
Chapter 33 I2C Controller
2.I2C Interface Registers
⇐ Bit no.
2 1 0
AAS GCA ADT
(R) (R) (R)
(0) (0) (0)
IBSR0
673