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[Bits 31 to 0] DMADA (DMA Destination Addr)*: Transfer destination address setting
These bits set the transfer destination address.
If DMA transfer is activated, data in this register is stored in the counter buffer of the DMA-dedicated address
counter and then the address is calculated according to the settings for the transfer operation. When the DMA
transfer is completed, the contents of the counter buffer are written back to this register and then DMA ends.
Thus, the address counter value during DMA operation cannot be read.
All registers have a dedicated reload register. When the register is used for a channel that is enabled for
reloading of the transfer source/transfer destination address register, the initial value is automatically written
back to the register when the transfer is completed. Other address registers are not affected.
•
When reset: Not initialized.
•
These bits are readable and writable. For this register, be sure to access these bits as 32-bit data.
•
If these bits are read during transfer, the address before the transfer is read. If they are read after transfer, the
next access address is read. Because the reload value cannot be read, it is not possible to read the transfer
address in real time.
Note:
Do not set any of the DMAC's registers using this register. DMA transfer is not possible for the DMAC's
registers themselves.
2.4 DMAC All-Channel Control Register (DMACR)
The DMAC all-channel control register (DMACR) controls the operation of the all five DMAC
channels. Be sure to access this register using byte length.
This section describes the configuration and functions of the DMAC all-channel control register
(DMACR).
■ Bit Configuration of DMAC All-Channel Control Register (DMACR)
Figure
2-5"Bit Configuration of the DMAC All-Channel Control Register (DMACR)" shows the bit configuration of
the DMAC all-channel control register (DMACR).
Figure 2-5 Bit Configuration of the DMAC All-Channel Control Register (DMACR)
bit
Address
000240
DMAE
H
bit
■ Detailed Bit of DMAC All-Channel Control Register (DMACR)
The following describes the bit functions of the DMAC all-channel control register (DMACR) bits.
[Bit 31] DMAE (DMA Enable): DMA operation enable
This bit controls the operation of all DMA channels.
If DMA operation is disabled with this bit, transfer operations on all channels are disabled regardless of the
start/stop settings for each channel and the operating status. Any channel carrying out transfer cancels the
requests and stops transfer at a block boundary. All start operations on each channel in a disabled state are
disabled.
If this bit enables DMA operation, start/stop operations are enabled for each channels. Simply enabling DMA
operation with this bit does not activate each channel.
31
30
29
28
27
26
-
-
PM01
DMAH[3:0]
15
14
13
12
11
10
-
-
-
-
-
-
25
24
23
22
21
20
-
-
-
-
9
8
7
6
5
4
-
-
-
-
-
-
Chapter 26 DMA Controller
2.DMA Controller (DMAC) Registers
Initial value
19
18
17
16
-
-
-
-
0XX00000XXXXXXXX
3
2
1
0
-
-
-
-
XXXXXXXXXXXXXXXX
B
351
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