Fujitsu MB91460 SERIES FR60 User Manual page 581

5.3 Read -> Write Operation
This section shows the operating timing for read -> write.
■ Operation Timing of Read -> Write
Figure 5-3 "Timing Chart for Read -> Write" shows the operation timing for (TYP3-0=0000
MCLK
A[31:0]
AS
CSn
RD
WRn
D[31:0]
• Setting of the W07/W06 bits of the AWR register enables 0-3 idle cycles to be inserted.
• Settings in the CS area on the read side are enabled.
• This idle cycle is inserted if the next access after a read access is write access or access to another area.
5.4 Write -> Write Operation
This section shows the operation timing for write -> write.
■ Write -> Write Operation
Figure 5-4 "Timing Chart for the Write -> Write Operation" shows the operation timing for (TYP3-0=0000
WR=0018 ).
H
Figure 5-3 Timing Chart for Read -> Write
Read Idle *
5.Operation of the Ordinary bus interface
, AWR=0048
B
Write
Chapter 31 External Bus
).
H
,
B
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