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FUJITSU SEMICONDUCTOR MN702-00009-2v0-E CONTROLLER MANUAL 8-BIT MICROCONTROLLER New 8FX MB95630H Series HARDWARE MANUAL...
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8-BIT MICROCONTROLLER New 8FX MB95630H Series HARDWARE MANUAL For the information for microcontroller supports, see the following website. http://edevice.fujitsu.com/micom/en-support/ FUJITSU SEMICONDUCTOR LIMITED...
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■ Sample Programs Fujitsu Semiconductor provides sample programs free of charge to operate the peripheral resources of the New 8FX family of microcontrollers. Feel free to use such sample programs to check the operational specifications and usages of Fujitsu microcontrollers.
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How to Use This Manual ■ Finding a Function The following methods can be used to search for details of a function in this manual: • Searching from CONTENTS CONTENTS lists the contents in this manual in the order of description. •...
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(including, without limitation, submersible repeater and artificial satellite). FUJITSU SEMICONDUCTOR shall not be liable for you and/or any third party for any claims or damages arising out of or in connection with above-mentioned uses of the products.
Page 9: Table Of Contents

CONTENTS CHAPTER 1 MEMORY ACCESS MODE .............. 1 Memory Access Mode ......................2 CHAPTER 2 CPU ....................3 Dedicated Registers ......................4 2.1.1 Register Bank Pointer (RP) .................... 6 2.1.2 Direct Bank Pointer (DP) ....................7 2.1.3 Condition Code Register (CCR) ..................9 General-purpose Register ....................
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5.1.3 Nested Interrupts ......................77 5.1.4 Interrupt Processing Time .................... 78 5.1.5 Stack Operation During Interrupt Processing ............... 79 5.1.6 Interrupt Processing Stack Area ................... 80 CHAPTER 6 I/O PORT ..................81 Overview ..........................82 Configuration and Operations .................... 83 CHAPTER 7 TIME-BASE TIMER ................
Page 11: Table Of Contents

11.3 Channel ........................... 141 11.4 Pins ..........................142 11.5 Interrupts ......................... 143 11.6 Operation of Interval Timer Function (One-shot Mode) ........... 144 11.7 Operation of Interval Timer Function (Continuous Mode) ..........146 11.8 Operation of Interval Timer Function (Free-run Mode) ............ 148 11.9 Operation of PWM Timer Function (Fixed-cycle Mode) ..........
Page 12: Table Of Contents

14.6.1 Operations in Asynchronous Mode (Operating Mode 0, 1) ........223 14.6.2 Operations in Synchronous Mode (Operating Mode 2) ..........227 14.6.3 Operations of LIN function (Operating Mode 3) ............231 14.6.4 Serial Pin Direct Access ..................... 234 14.6.5 Bidirectional Communication Function (Normal Mode) ..........235 14.6.6 Master/Slave Mode Communication Function (Multiprocessor Mode) .......
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18.2 Configuration ........................307 18.3 Channel ........................... 309 18.4 Pins ..........................310 18.5 Interrupt ........................... 311 18.6 Operations and Setting Procedure Example ..............312 18.6.1 8-bit PPG Independent Mode ..................313 18.6.2 8-bit Prescaler + 8-bit PPG Mode ................315 18.6.3 16-bit PPG Mode ......................
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CHAPTER 21 MULTI-PULSE GENERATOR ............377 21.1 Overview .......................... 378 21.2 Block Diagram ......................... 381 21.3 Pins ..........................389 21.4 Interrupts ......................... 390 21.5 Operations ........................392 21.5.1 Operation of Position Detection .................. 394 21.5.2 Operation of Data Write Control Unit ................396 21.5.3 Operation of 16-bit MPG Output Data Buffer Register (Upper/Lower) (OPDBRHx/OPDBRLx) ....................
Page 15: Table Of Contents

22.6.2 Operations in Operation Mode 1 ................470 22.7 Registers ......................... 476 22.7.1 UART/SIO Serial Mode Control Register 1 ch. n (SMC1n) ........477 22.7.2 UART/SIO Serial Mode Control Register 2 ch. n (SMC2n) ........479 22.7.3 UART/SIO Serial Status and Data Register ch. n (SSRn) .......... 481 22.7.4 UART/SIO Serial Input Data Register ch.
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26.4.5 Toggle Bit2 Flag (DQ2) ....................548 26.5 Programming/Erasing Flash Memory ................549 26.5.1 Placing Flash Memory in Read/Reset State ............... 550 26.5.2 Programming Data to Flash Memory ................551 26.5.3 Erasing All Data from Flash Memory (Chip Erase) ............. 553 26.5.4 Erasing Specific Data from Flash Memory (Sector Erase) .........
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Bit Manipulation Instructions (SETB, CLRB) ..............621 MC-8FX Instructions ....................622 Instruction Map ........................ 625 xiii...
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Major revisions in this edition A change on a page is indicated by a vertical line drawn on the left of that page. Page Revisions (For details, see their respective pages.) CHAPTER 3 CLOCK Corrected the connection between the main CR PLL clock CONTROLLER oscillator circuit and the PLLC control register (PLLC).
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Page Revisions (For details, see their respective pages.) CHAPTER 15 8/10-BIT A/D Corrected the register name of the ADDH and ADDL CONVERTER registers. 15.2 Configuration of 8/10-bit A/D A/D converter data registers (ADDH, ADDL) Converter 8/10-bit A/D converter data registers (ADDH, ADDL) Corrected the register name of the ADC1 register.
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Page Revisions (For details, see their respective pages.) Corrected the register name of the IBCR0n register. CHAPTER 24 I C BUS INTERFACE C bus control register 0 24.3 Channel ■ Channel of I C Bus Interface C bus control register 0 ch. n Table 24.3-2 Corrected the register name of the IBCR1n register.
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xviii...
Page 23: Chapter 1 Memory Access Mode

CHAPTER 1 MEMORY ACCESS MODE This chapter describes the memory access mode. Memory Access Mode MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 24: Memory Access Mode

Reserved. Do not set mode data to any value other than 0x00. After a reset is released, the CPU fetches mode data first. The CPU then fetches the reset vector after the mode data. It starts executing instructions from the address set in the reset vector. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 25: Chapter 2 Cpu

CHAPTER 2 This chapter describes the functions and operations of the CPU. Dedicated Registers General-purpose Register Placement of 16-bit Data in Memory MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 26: Dedicated Registers

(8-bit) data. For byte-length arithmetic and transfer operations, only the lower eight bits (AL) of the accumulator are used with the upper eight bits (AH) left unchanged. The initial value set immediately after a reset is "0x0000". FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
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(0x0078). Note that the condition code register (CCR) is a part of the program status register and cannot be accessed independently. Refer to the "F MC-8FX Programming Manual" for details on using the dedicated registers. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 28: Register Bank Pointer (rp)

PS with the "MOVW A,PS" instruction. Values can also be directly written to and read from the two pointers by accessing "0x0078", the mirror address of the register bank pointer. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 29: Direct Bank Pointer (dp)

0x0200 to 0x027F 0b100 0x0080 to 0x00FF 0x0280 to 0x02FF 0b101 0x0300 to 0x037F 0b110 0x0380 to 0x03FF 0b111 0x0400 to 0x047F *: The available access area varies among products. For details, refer to the device data sheet. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
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Table 2.1-2 Direct Address Instruction List Applicable instructions CLRB dir:bit SETB dir:bit BBC dir:bit,rel BBS dir:bit,rel MOV A,dir CMP A,dir ADDC A,dir SUBC A,dir MOV dir,A XOR A,dir AND A,dir OR A,dir MOV dir,#imm CMP dir,#imm MOVW A,dir MOVW dir,A FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 31: Condition Code Register (ccr)

This flag indicates whether the result of an operation has caused an overflow, with the operand used in the operation being regarded as an integer expressed as a complement of two. If an overflow occurs, the overflow flag is set to "1"; otherwise, it is set to "0". MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
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Table 2.1-3 Interrupt Levels Interrupt level Priority High Low (No interrupt) The interrupt level bits (IL[1:0]) are usually "0b11" when the CPU does not service an interrupt (with the main program running). For details of interrupts, see "5.1 Interrupts". FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 33: General-purpose Register

The number of banks available is restricted by Bank 0 the available RAM size. Memory area For information on the general-purpose register area available on each product, see "■ AREAS FOR SPECIFIC APPLICATIONS" in the device data sheet. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
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512 bytes or above. Therefore, when using a program development tool such as a C compiler to set a general-purpose register area, ensure that the area used as a general-purpose register area does not exceed the size of RAM installed. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 35: Placement Of 16-bit Data In Memory

Storage state of 16-bit data in the stack When 16-bit register data is saved in a stack on an interrupt, the upper byte is stored at a lower address in the same way as 16-bit data specified by an operand. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
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CHAPTER 2 CPU MB95630H Series 2.3 Placement of 16-bit Data in Memory FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 37: Chapter 3 Clock Controller

Overview Oscillation Stabilization Wait Time Registers Clock Modes Operations in Low Power Consumption Mode (Standby Mode) Clock Oscillator Circuit Overview of Prescaler Configuration of Prescaler Operation of Prescaler 3.10 Notes on Using Prescaler MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 38: Overview

CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.1 Overview Overview The New 8FX family has a built-in clock controller that optimizes its power consumption. It supports both of the external main clock and the external subclock. The clock controller enables/disables clock oscillation, enables/disables the supply of clock signals to the internal circuit, selects the clock source, and controls the internal CR oscillator and frequency divider circuits.
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(1): Main clock (F (5): Main CR clock (F (9): Main CR PLL clock (F MCRPLL (2): Subclock (F (6): Sub-CR clock (F (3): Main clock (7): Source clock (SCLK) (4): Subclock (8): Machine clock (MCLK) MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
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● Standby control register (STBC) This register controls the transition from RUN state to standby mode, the setting of pin states in stop mode, time-base timer mode, or watch mode, and the generation of software resets. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
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● Oscillation stabilization wait time setting register (WATR) This register sets the oscillation stabilization wait times for the main clock and subclock. ● Standby control register 2 (STBC2) This register controls the deep standby mode. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 42: Clock Modes

The machine clock is generated by dividing the subclock by two. Sub-CR clock mode The machine clock is generated by dividing the sub-CR clock by two. In any clock mode, the frequency of a selected clock can be divided. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
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In addition, with the hardware watchdog timer already started, the watchdog timer operates also in standby mode, depending on the settings of the non-volatile register (NVR) interface. For details of the non-volatile register (NVR) interface, see "CHAPTER 27 NON-VOLATILE REGISTER (NVR) INTERFACE". MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
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*6: The state of the Flash memory in a standby mode can be selected from two options, normal state and low- power state, by the deep standby mode control bit in the standby control register 2 (STBC2:DSTBYX). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
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*6: The state of the Flash memory in a standby mode can be selected from two options, normal state and low- power state, by the deep standby mode control bit in the standby control register 2 (STBC2:DSTBYX). MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 46: Oscillation Stabilization Wait Time

Power-on reset Initial value: (2 -2)/F : main clock frequency) Main clock Other than power-on reset Register settings (WATR:MWT[3:0]) Power-on reset Initial value: (2 -2)/F : subclock frequency) Subclock Other than power-on reset Register settings (WATR:SWT[3:0]) FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
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For details on state transition, see "3.4 Clock Modes" and "3.5 Operations in Low Power Consumption Mode (Standby Mode)". MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
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Sub-CR clock > Subclock > Main clock • Subclock mode Sub-CR clock > Main CR clock or main clock > Main CR PLL clock • Sub-CR clock mode Main CR clock or main clock > Subclock > Main CR PLL clock FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 49: Registers

System clock control register 3.3.1 PLLC PLL control register 3.3.2 WATR Oscillation stabilization wait time setting register 3.3.3 STBC Standby control register 3.3.4 SYCC2 System clock control register 2 3.3.5 STBC2 Standby control register 2 3.3.6 MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 50: System Clock Control Register (sycc)

The machine clock is generated from the source clock according to the divide ratio set by these bits. bit1:0 Details Writing "00" Source clock (no division) Writing "01" Source clock/4 Writing "10" Source clock/8 Writing "11" Source clock/16 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 51: Pll Control Register (pllc)

PLL clock oscillation has stopped. Reading "1" Indicates that the main CR PLL clock oscillation wait time is over. [bit3:0] Undefined bits Their read values are always "0". Writing values to these bits has no effect on operation. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 52: Oscillation Stabilization Wait Time Setting Register (watr)

"1". These bits can be modified when the subclock is stopped with the subclock oscillation stop bit in the system clock control register 2 (SYCC2:SOSCE) set to "0" in main clock mode, main CR clock mode, main CR PLL clock mode, or sub-CR clock mode. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
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"1". These bits can be modified when the main clock is stopped with the main clock oscillation stop bit in the system clock control register 2 (SYCC2:MOSCE) set to "0" in main CR clock mode, main CR PLL clock mode, subclock mode, or sub-CR clock mode. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 54: Standby Control Register (stbc)

An external pin becomes high impedance in stop mode, time-base timer mode and watch mode. Writing "1" (A pin for which connection to a pull-up resistor has been selected in the pull-up register is pulled up.) FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
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(SRST) and watch bit (TMD), are set to "1" together, the order of priority for such bits is as follows: (1) Software reset bit (SRST) (2) Stop bit (STP) (3) Watch bit (TMD) (4) Sleep bit (SLP) When released from standby mode, the device returns to the normal operating state. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 56: System Clock Control Register 2 (sycc2)

Indicates that the clock controller is in the main CR clock oscillation stabilization wait state or Reading "0" that the main CR clock oscillation has stopped. Reading "1" Indicates that the main CR clock oscillation wait time is over. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
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When the current clock mode is subclock mode or sub-CR clock mode, writing "1" to this bit has no effect on operation. bit0 Details Writing "0" Disables the main CR clock oscillation. Writing "1" Enables the main CR clock oscillation. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 58: Standby Control Register 2 (stbc2)

Refer to "■ ELECTRICAL CHARACTERISTICS" in the device data sheet for the difference between the deep standby mode and the normal standby mode in power consumption. • Do not make the device transit to deep standby mode when a Flash command sequence (except read/reset) has been invoked. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 59: Clock Modes

CR clock mode or main CR PLL clock mode to subclock mode or sub-CR clock mode. In subclock mode or sub-CR clock mode, writing "1" to SYCC2:MOSCE, SYCC2:MCRE or PLLC:MPEN cannot enable the main clock, the main CR clock, or the main CR PLL clock respectively. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
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(or main CR PLL clock) stabilization stabilization stabilization oscillation stabilization wait time wait time wait time (13) (18) (17) Sub-CR clock oscillation stabilization (20) wait time (19) Subclock mode Sub-CR clock mode (15) (16) Subclock oscillation stabilization wait time (14) FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
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PLL control register (PLLC:MPRDY) is "1", the device transits to main CR PLL clock mode immediately after the clock mode select bits (SYCC:SCS[2:0]) are set to "0b111". Sub-CR clock Same as (1) and (2) (10) (11) Subclock Same as (3) and (4) (12) MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
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(15) Subclock Same as (3) and (4) (16) Main CR clock/ (17) Main CR PLL Same as (13) clock Subclock (18) Main clock Same as (14) (19) Sub-CR clock Same as (1) and (2) (20) FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 63: Operations In Low Power Consumption Mode (standby Mode)

I/O port or a peripheral function pin to high impedance in stop mode, time-base timer mode or watch mode. Refer to the device data sheet for the states of all pins in standby mode. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 64: Notes On Using Standby Mode

(CCR) of the CPU. If interrupts are not to be accepted according to the settings of CCR, the device resumes instruction execution from the instruction following the one executed before the device transits to standby mode. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
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For details of the Flash recovery wait time, see Table 3.5-2. For the difference between deep standby mode and normal standby mode in power consumption, refer to "■ ELECTRICAL CHARACTERISTICS" in the device data sheet. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
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(STBC:TMD) in main clock mode, main CR clock mode, Time-base timer mode or main CR PLL clock mode. The device returns to the RUN state in response to an interrupt from a peripheral function. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
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The device transits to watch mode when "1" is written to the watch bit in the standby control register (STBC:TMD) in subclock mode or sub-CR clock mode. Watch mode The device returns to the RUN state in response to an interrupt from a peripheral function. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
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In main clock mode, main CR clock mode, or main CR PLL clock mode Maximum: 10 SCLK + 150 µs + 6 MCLK • In subclock mode or sub-CR clock mode Maximum: 2 SCLK + 150 µs + 6 MCLK FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
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During the Flash recovery wait time, the device transits to sleep mode. (The CPU stops its operation; the peripheral function resumes its operation.) However, if a program is being executed on the RAM, no Flash recovery wait time occurs. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 70: Sleep Mode

Flash recovery wait time elapses. However, if a program is being executed on the RAM, no Flash recovery wait time occurs. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 71: Stop Mode

When the oscillation stabilization wait time is longer than the Flash recovery wait time After the oscillation stabilization wait time elapses, the device returns to the RUN state. However, if a program is being executed on the RAM, no Flash recovery wait time occurs. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
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Therefore, some settings of that peripheral function, such as the initial interval time of the interval timer, become undefined. Initialize that peripheral function if necessary after releasing the device from stop mode. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 73: Time-base Timer Mode

Flash recovery wait time elapses. However, if a program is being executed on the RAM, no Flash recovery wait time occurs. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
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Therefore, some settings of that peripheral function, such as the initial interval time of the interval timer, become undefined. Initialize that peripheral function if necessary after releasing the device from time-base timer mode. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 75: Watch Mode

Therefore, some settings of that peripheral function, such as the initial interval time of the interval timer, become undefined. Initialize that peripheral function if necessary after releasing the device from watch mode. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 76: Clock Oscillator Circuit

X0A pin while leaving the X1A pin unconnected. Figure 3.6-2 Sample Connection of External Clocks X1 open Inverted X0 input to X1 Main clock Subclock Main clock Subclock oscillator circuit oscillator circuit oscillator circuit oscillator circuit Open Open Open FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 77: Overview Of Prescaler

, or F ) of the time- MCRPLL MCRPLL base timer. • 8/16-bit composite timer • 8/10-bit A/D converter • 8/16-bit PPG • 16-bit PPG timer • 16-bit reload timer • UART/SIO dedicated baud rate generator MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 78: Configuration Of Prescaler

■ Output Clock The prescaler supplies clocks to the following peripheral functions: • 8/16-bit composite timer • 8/10-bit A/D converter • 8/16-bit PPG • 16-bit PPG timer • 16-bit reload timer • UART/SIO dedicated baud rate generator FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 79: Operation Of Prescaler

Count Clock Sources Generated by Prescaler (F Frequency Count clock source = 4 MHz, frequency MCLK= 4 MHz) MCLK/2 2 MHz MCLK/4 1 MHz MCLK/8 0.5 MHz MCLK/16 0.25 MHz MCLK/32 125 kHz 62.5 kHz 31.25 kHz MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 80

MCLK/16 0.5 MHz 0.625 MHz 0.75 MHz 1 MHz MCLK/32 0.25 MHz 0.3125 MHz 0.375 MHz 0.5 MHz 125 kHz 156.25 kHz 187.5 kHz 0.25 MHz MCRPLL 62.5 kHz 78.125 kHz 93.75 kHz 125 kHz MCRPLL FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 81: Notes On Using Prescaler

The prescaler count value affects the following peripheral functions: • 8/16-bit composite timer • 8/10-bit A/D converter • 8/16-bit PPG • 16-bit PPG timer • 16-bit reload timer • UART/SIO dedicated baud rate generator MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
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CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.10 Notes on Using Prescaler FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 83: Chapter 4 Reset

CHAPTER 4 RESET This section describes the reset operation. Reset Operation Register Notes on Using Reset MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 84: Reset Operation

After the watchdog timer starts, a watchdog reset is generated if the watchdog timer is not cleared within a predetermined period of time. ● Power-on reset A power-on reset is generated when the power is switched on. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
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"L" level while resetting it. However, the function to output "L" level is not provided for external reset in the reset pin. For details of the reset input function and the reset output function setting, see "CHAPTER 29 SYSTEM CONFIGURATION CONTROLLER". MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
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RAM access ends. This function prevents a word-data write operation from being interrupted by a reset while data of two bytes is being written. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 87

Connect a pull-up resistor to a pin that becomes high impedance during a reset to prevent the device from malfunctioning. For details of the states of all pins during a reset, refer to the device data sheet. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 88: Register

CHAPTER 4 RESET MB95630H Series 4.2 Register Register This section provides details of the register for reset. Table 4.2-1 List of Register for Reset Register Register name Reference abbreviation RSRR Reset source register 4.2.1 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 89: Reset Source Register (rsrr)

A read access or a write access (writing "0" or "1") to this bit sets it to "0". bit2 Details Read access Sets this bit to "0". Being set to "1" Indicates that the a power-on reset or a low-voltage detection reset (optional) has occurred. Write access Sets this bit to "0". MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 90

Indicates that the a software reset has occurred. Write access Sets this bit to "0". Note: Since reading the reset source register clears its contents, save the contents of this register to the RAM before using those contents for calculation. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 91

When this bit is set to "1", that indicates one of the following reset has occurred: an external reset, a watchdog reset, a power-on reset or a low-voltage detection reset (optional). SWR: When this bit is set to "1", that indicates that a software reset has occurred. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 92: Notes On Using Reset

The type of reset source determines which bit in the reset source register (RSRR) is to be initialized. • The oscillation stabilization wait time setting register (WATR) of the clock controller can only be initialized by a power-on reset. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 93: Chapter 5 Interrupts

CHAPTER 5 INTERRUPTS This chapter describes the interrupts. Interrupts MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 94: Interrupts

This section describes the interrupts. ■ Overview of Interrupts The New 8FX family has 24 interrupt request inputs for respective peripheral functions, for each of which an interrupt level can be set independently to each other. When a peripheral function generates an interrupt request, the interrupt request is output to the interrupt controller.
Page 95: Interrupt Level Setting Registers (ilr0 To Ilr5)

The interrupt level setting registers assign a pair of bits to every interrupt request. The values of interrupt level setting bits in these registers represent the priority of an interrupt request (interrupt level: 0 to 3) in interrupt processing. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 96

Table 5.1-1 Relationships Between Interrupt Level Setting Bits and Interrupt Levels LXX[1:0] Interrupt level Priority Highest Lowest (No interrupt) XX:00 to 23 Number of an interrupt request While the main program is being executed, the interrupt level bits in the condition code register (CCR:IL[1:0]) are "0b11". FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 97: Interrupt Processing

IL value? I flag = 1? Execute main program Interrupt service routine Clear interrupt request Save PC and PS to stack Restore PC and PS Execute interrupt processing interrupt vector RETI Update IL in PS MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 98

(writing "0" to the interrupt request flag bit) in the interrupt service routine. The low power consumption mode (standby mode) is released by an interrupt. For details, see "3.5 Operations in Low Power Consumption Mode (Standby Mode)". FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 99: Nested Interrupts

CPU resumes executing the program interrupted. In addition, the values of the condition code register (CCR) return to the ones existing before the interrupt due to the restoration of the value of the program status (PS). MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 100: Interrupt Processing Time

(17 machine clock cycles), the interrupt processing time spans 26 machine clock cycles. The span of a machine clock cycle varies depending on the clock mode and main clock speed change (gear function). For details, see "CHAPTER 3 CLOCK CONTROLLER". FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 101: Stack Operation During Interrupt Processing

Since the value of the accumulator (A) and that of the temporary accumulator (T) are not automatically saved to the stack, use the PUSHW and POPW instructions to save and restore the values of A and T. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 102: Interrupt Processing Stack Area

POPW instruction, etc. in ascending order of addresses. If the address value of the stack area used decreases due to nested interrupts or subroutine calls, do not let the stack area overlap the data area and the general-purpose register area, both of which retain other data. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 103: Chapter 6 I/o Port

CHAPTER 6 I/O PORT This chapter describes the configuration and operations of the I/O port. Overview Configuration and Operations MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 104

A/D input disable register (upper)* AIDRH A/D input disable register (lower)* AIDRL *: Refer to "■ I/O MAP" in the device data sheet for the availability of the A/D input disable register (upper) and A/D input disable register (lower). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 105: Configuration And Operations

• General-purpose I/O pins/peripheral function I/O pins • Port x data register (PDRx) • Port x direction register (DDRx) • Port x pull-up register (PULx) • A/D input disable register (upper) (AIDRH) • A/D input disable register (lower) (AIDRL) MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 106

• Reading the PDRx register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDRx register, the PDRx register value is returned. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 107

Setting the bit in the PULx register to "1" makes the pull-up resistor be internally connected to the pin. When the pin output is "L" level, the pull-up resistor is disconnected regardless of the value of the PULx register. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 108

CHAPTER 6 I/O PORT MB95630H Series 6.2 Configuration and Operations FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 109: Chapter 7 Time-base Timer

CHAPTER 7 TIME-BASE TIMER This chapter describes the functions and operations of the time-base timer. Overview Configuration Interrupt Operations and Setting Procedure Example Register Notes on Using Time-base Timer MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 110

= 0.5 s *2: F = 4 MHz = 0.25 s *3: F = 8 MHz MCRPLL PLL multiplication rate = 2 PLL multiplication rate = 4 MHz 2 = 8 MHz = 0.125 s MCRPLL FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 111: Configuration

Stops main clock oscillation or main CR clock oscillation clear circuit selector Time-base timer interrupt TBIF TBIE TBC3 TBC2 TBC1 TBC0 TCLR Time-base timer control register (TBTC) : Main clock : Main CR clock : Main CR PLL clock MCRPLL MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 112

The time-base timer uses the main clock divided by two, the main CR clock or the main CR PLL clock as its input clock (count clock). ■ Output Clock The time-base timer supplies clocks to the clock supervisor counter, the software watchdog timer and the prescaler. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 113: Interrupt

TBIF bit at the same time (TBTC:TBIF = 0). Table 7.3-1 Interrupt of Time-base Timer Item Description Interrupt condition The interval time set by "TBTC:TBC[3:0]" has elapsed. Interrupt flag TBTC:TBIF Interrupt enable TBTC:TBIE MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 114: Operations And Setting Procedure Example

The device transits from the main clock mode, the main CR clock mode or the main CR PLL clock mode to the subclock mode or the sub-CR clock mode. • At power-on • At low-voltage detection reset FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 115

: Time-base timer interrupt request flag bit in time-base timer control register • TBTC:TBIE : Time-base timer interrupt request enable bit in time-base timer control register • STBC:SLP : Sleep bit in standby control register • STBC:STP : Stop bit in standby control register MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 116

*: For details of the interrupt level setting register (ILR), refer to "CHAPTER 5 INTERRUPTS" in this hardware manual and "■ INTERRUPT SOURCE TABLE" in the device data sheet. ● Processing interrupts 1. Clear the interrupt request flag. (TBTC:TBIF = 0) 2. Clear the counter. (TBTC:TCLR = 1) FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 117

CHAPTER 7 TIME-BASE TIMER MB95630H Series 7.5 Register Register This section describes the register of the time-base timer. Table 7.5-1 List of Time-base Timer Register Register Register name Reference abbreviation TBTC Time-base timer control register 7.5.1 MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 118: Time-base Timer Control Register (tbtc)

Writing "0" Disables the time-base timer interrupt request. Writing "1" Enables the time-base timer interrupt request. [bit5] Undefined bit The read value is always "0". Writing a value to this bit has no effect on operation. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 119

Clears all bits in the counter of the time-base timer to "1". Note: When the output of the time-base timer is selected as the count clock for the software watchdog timer, clear the time-base timer with this bit also clears the software watchdog timer. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 120: Notes On Using Time-base Timer

However, since the software watchdog timer counter is also cleared at the same time as the clock for the software watchdog timer returns to the initial state, the software watchdog timer operates in its normal cycle. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 121

CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER This chapter describes the functions and operations of the watchdog timer. Overview Configuration Operations and Setting Procedure Example Register Notes on Using Watchdog Timer MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 122

Sub-CR timer 0bXX1* (software watchdog timer) or 437 ms 2.62 s (sub-CR clock = 50 kHz to 150 kHz) hardware watchdog timer* *1: X = 0 or 1 *2: CS[1:0] = 0b00, CSP = 1 (read-only) FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 123

Sleep mode starts Counter clear Stop mode starts control circuit Time-base timer/watch mode starts Stopping or running in stop mode : Main clock : Main CR clock : Main CR PLL clock MCRPLL : Subclock : Sub-CR clock MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 124

This register performs setup for activating/clearing the watchdog timer counter as well as for selecting the count clock. ■ Input Clock The watchdog timer uses the output clock of the time-base timer, of the watch prescaler or of the sub-CR timer as the input clock (count clock). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 125

In the case of activating the hardware watchdog timer with its operation in standby mode enabled, whether the device transits to standby mode or wakes up from standby mode, the counter of the watchdog timer is not cleared and the watchdog timer continues its operation. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 126

When a watchdog reset is generated in subclock mode, the timer starts operating in main clock mode after the oscillation stabilization wait time has elapsed. The reset signal is output during this oscillation stabilization wait time. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 127

"0xA596" and "0xA597" enables the hardware watchdog timer in all modes. See "CHAPTER 27 NON-VOLATILE REGISTER (NVR) INTERFACE" for details of the watchdog timer selection ID. 2. Clear the watchdog timer. (WDTC:WTE[3:0] = 0b0101) MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 128: Chapter 8 Hardware/software Watchdog Timer, Register

CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER MB95630H Series 8.4 Register Register This section describes the register of the watchdog timer. Table 8.4-1 List of Watchdog Timer Register Register Register name Reference abbreviation WDTC Watchdog timer control register 8.4.1 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 129: Watchdog Timer Control Register (wdtc)

This is a read-only bit used to confirm the start/stop of the hardware watchdog timer. bit4 Details Indicates that the hardware watchdog timer has stopped (The software watchdog timer can be Reading "0" activated). Reading "1" Indicates that the hardware watchdog timer has been activated. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 130

Writing "0101" to these bits in the second write access or later after a reset clears the software watchdog timer. Writing a value Has no effect on operation. other than "0101" Note: Using the read-modify-write (RMW) type of instruction to access the WDTC register is prohibited. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 131: Notes On Using Watchdog Timer

CPU wakes up from stop mode in subclock mode or sub-CR clock mode. Take account of the setting of the subclock stabilization wait time when selecting the subclock. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 132

CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER MB95630H Series 8.5 Notes on Using Watchdog Timer FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 133: Chapter 9 Watch Prescaler

CHAPTER 9 WATCH PRESCALER This chapter describes the functions and operations of the watch prescaler. Overview Configuration Interrupt Operations and Setting Procedure Example Register Notes on Using Watch Prescaler MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 134

1.311 s n=17 2.621 s *1: 2/F =20 µs when F =100 kHz *2: 2/F =61.035 µs when F =32.768 kHz Note: Refer to the device data sheet for the accuracy of the sub-CR clock frequency. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 135

Watchdog timer clear Resets, or stops Counter clear Interval timer subclock oscillation or circuit selector sub-CR clock oscillation Interrupt of watch prescaler WTIF WTIE WTC2 WTC1 WTC0 WCLR Watch prescaler control register (WPCR) : Subclock : Sub-CR clock MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 136

The watch prescaler uses the subclock divided by two or the sub-CR clock divided by two as its input clock (count clock). ■ Output Clock The watch prescaler supplies its clock to the software watchdog timer. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 137

WPCR register to "1" and clear the WTIF bit in the same register simultaneously. Table 9.3-1 Interrupt of Watch Prescaler Item Description Interrupt condition Interval time set by "WPCR:WTC[2:0]" has elapsed. Interrupt flag WPCR:WTIF Interrupt enable WPCR:WTIE MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 138

When the subclock oscillation and the sub-CR clock oscillation are enabled, and the oscillation stabilization wait time elapses, the subclock is selected as the input clock of the watch prescaler. • In subclock mode Only the subclock is used as the input clock of the watch prescaler. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 139

: Watch prescaler interrupt request flag bit in watch prescaler control register • WPCR:WTIE : Watch prescaler interrupt request enable bit in watch prescaler control register • STBC:SLP : Sleep bit in standby control register • STBC:STP : Stop bit in standby control register MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 140

*: For details of the interrupt level setting register (ILR), refer to "CHAPTER 5 INTERRUPTS" in this hardware manual and "■ INTERRUPT SOURCE TABLE" in the device data sheet. ● Processing interrupts 1. Clear the interrupt request flag. (WPCR:WTIF = 0) 2. Clear the counter. (WPCR:WCLR = 1) FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 141

CHAPTER 9 WATCH PRESCALER MB95630H Series 9.5 Register Register This section describes the register of the watch prescaler. Table 9.5-1 List of Watch Prescaler Register Register Register name Reference abbreviation WPCR Watch prescaler control register 9.5.1 MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 142: Watch Prescaler Control Register (wpcr)

Details Writing "0" Disables the watch prescaler interrupt request. Writing "1" Enables the watch prescaler interrupt request. [bit5:4] Undefined bits Their read values are always "0". Writing values to these bits has no effect on operation. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 143

Clears all bits in the counter of the watch prescaler to "1". Note: When the output of the watch prescaler is selected as the count clock of the software watchdog timer, clearing the watch prescaler with this bit also clears the software watchdog timer. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 144: Notes On Using Watch Prescaler

However, since the software watchdog timer counter is also cleared at the same time as the clock for the software watchdog timer returns to the initial state, the software watchdog timer operates in its normal cycle. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 145: Chapter 10 Wild Register Function

CHAPTER 10 WILD REGISTER FUNCTION This chapter describes the functions and operations of the wild register function. 10.1 Overview 10.2 Configuration 10.3 Operations 10.4 Registers 10.5 Typical Hardware Connection Example MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 146

ROM data can be replaced with modification data set in the registers. Data of up to three different addresses can be modified. The wild register function can be used to debug a program after creating the mask and to patch bugs in the program. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 147

Memory area block Wild register address setting register (WRAR) Wild register data setting register (WRDR) Access control circuit Wild register address compare enable register (WREN) Wild register data test setting register (WROR) Memory space MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 148

(WRAR). If they match, the circuit outputs the data from the wild register data setting register (WRDR) to the data bus. The operation of the control circuit block is controlled by the wild register address compare enable register (WREN). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 149: Operations

The wild register function can be applied to all address space except the address "0x0078". Since the address "0x0078" is used as a mirror address for the register bank pointer and the direct bank pointer, this address cannot be patched. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 150

Table 10.4-2 Wild Register Numbers Corresponding to Wild Register Address Setting Registers and Wild Register Data Setting Registers Wild register Wild register address setting register Wild register data setting register number (WRAR) (WRDR) WRAR0 WRDR0 WRAR1 WRDR1 WRAR2 WRDR2 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 151: Wild Register Data Setting Registers (wrdr0 To Wrdr2)

The read access to one of these bits is enabled only when the data test setting bit in the wild register data test setting register (WROR) corresponding to the bit to be read is set to "1". MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 152: Wild Register Address Setting Registers (wrar0 To Wrar2)

These bits set the address to be amended by the wild register function. The address to be assigned to amendment data is set to these bits. The address is to be specified according to the wild register number corresponding to a wild register address setting register. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 153: Wild Register Address Compare Enable Register (wren)

• EN1 corresponds to wild register number 1. • EN2 corresponds to wild register number 2. bit2/bit1/bit0 Details Writing "0" Disables the operation of the wild register function. Writing "1" Enables the operation of the wild register function. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 154: Wild Register Data Test Setting Register (wror)

• DRR1 corresponds to wild register number 1. • DRR2 corresponds to wild register number 2. bit2/bit1/bit0 Details Writing "0" Disables reading from the wild register data setting register. Writing "1" Enables reading from the wild register data setting register. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 155: Typical Hardware Connection Example

10.5 Typical Hardware Connection Example 10.5 Typical Hardware Connection Example Below is an example of typical hardware connection for the application of the wild register function. ■ Hardware Connection Example Figure 10.5-1 Typical Hardware Connection Example EEPROM (Storing correction program) MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 156

CHAPTER 10 WILD REGISTER FUNCTION MB95630H Series 10.5 Typical Hardware Connection Example FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 157: Chapter 11 8/16-bit Composite Timer

11.9 Operation of PWM Timer Function (Fixed-cycle Mode) 11.10 Operation of PWM Timer Function (Variable-cycle Mode) 11.11 Operation of PWC Timer Function 11.12 Operation of Input Capture Function 11.13 Operation of Noise Filter 11.14 Registers 11.15 Notes on Using 8/16-bit Composite Timer MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 158

8-bit PWM signal of variable cycle and duty depending on the cycle and "L" pulse width specified by registers. In this operating mode, since the two 8-bit counters have to be used separately, the composite timer cannot operate as a 16-bit counter. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 159

In free-run mode, the counter transfers its value to a register to generate an interrupt immediately after the detection of an edge. Afterward, unlike in clear mode, the counter continues to count without being cleared to "0x00". MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 160

For details, refer to the device data sheet. In this chapter, "n" in a pin name and a register abbreviation represents the channel number. For details of pin names, register names and register abbreviations of a product, refer to the device data sheet. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 161

16-bit counter. ● 8-bit comparator The comparator compares the value in the 8/16-bit composite timer data register and that in the counter. It incorporates a latch that temporarily stores the 8/16-bit composite timer data register value. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 162

LIN-UART". In addition, the TII0 pin for any timer other than timer 00 is internally fixed at "0". ■ Input Clock The 8/16-bit composite timer uses the output clock from the prescaler as its input clock (count clock). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 163: Channel

The following table lists the external pins on a channel. Table 11.3-1 External Pins of 8/16-bit Composite Timer Pin name Pin function TOn0 Timer n0 output TOn1 Timer n1 output Timer n0 input and timer n1 input MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 164: Pins

(variable-cycle mode) is selected, the input function of this pin can also be used. To use the input function mentioned above, set the bit in the port direction register corresponding to ECn pin to "0" to make the pin as an input port. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 165

16-bit detection in the input (variable-cycle mode), except operation capture operation, except in 16-bit operation in 16-bit operation Interrupt flag Tn1CR1:IF Tn1CR1:IF Tn1CR1:IR Interrupt enable Tn1CR1:IE and Tn1CR0:IFE Tn1CR1:IE and Tn1CR0:IFE Tn1CR1:IE MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 166: Operation Of Interval Timer Function (one-shot Mode)

(comparison data storage latch) in the comparator when the counter starts counting. Do not write "0x00" to the 8/16-bit composite timer data register. Figure 11.6-2 shows the operation of the interval timer function in 8-bit operation. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 167

Reactivated with output initial value unchanged ("0") Timer output pin For initial value "1" on activation *: If the Tn0DR/Tn1DR data register value is modified during operation, the new value is used from the next active cycle. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 168: Operation Of Interval Timer Function (continuous Mode)

Do not write "0x00" to the 8/16-bit composite timer data register while the counter is counting. When the timer stops operating, the timer output bit (TMCRn:TO0/TO1) holds the last value. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 169

*1: If the Tn0DR/Tn1DR data register value is modified during operation, the new value is used from the next active cycle. *2: The counter is cleared and the data register settings are loaded into the comparison data latch whenever a match is detected during operation. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 170: Operation Of Interval Timer Function (free-run Mode)

Do not write "0x00" to the 8/16-bit composite timer data register. When the timer stops operation, the timer output bit (TMCRn:TO0/TO1) holds the last value. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 171

Activated Matched Matched Matched Matched Counter value match* Timer output pin *: Even though a match is detected during operation, the counter is not cleared. The data register settings are reloaded into the comparison data latch. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 172: Operation Of Pwm Timer Function (fixed-cycle Mode)

When the timer stops operation, the timer output bit (TMCRn:TO0/TO1) holds the last value. In the output waveform immediately after activation of the timer (write "1" to the STA bit), the "H" pulse is one count clock shorter than the value set in the Tn0DR/Tn1DR register. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 173

Counter value 0x00 0xFF 0x00 "H" PWM waveform One count width "L" Note: When the PWM function has been selected, the timer output pin holds the level at the point when the counter stops (Tn0CR1/Tn1CR1:STA = 0). MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 174: Operation Of Pwm Timer Function (variable-cycle Mode)

When the timer stops operating, the timer output bit (TMCRn:TO0) holds the last output value. If the 8/16-bit composite timer data register is modified during operation, the data written will become valid from the cycle immediately after the detection of a synchronous match. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 175

"H" PWM waveform "L" Tn0DR register value: 0x00", Tn1DR register value: "0xFF" (duty ratio = 99.6%) Counter timer n0 value 0x00 0x00 Counter timer n1 value 0x00 0xFF, 0x00 "H" PWM waveform "L" One count width MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 176: Operation Of Pwc Timer Function

In addition, the timer output is inverted due to the overflow. The timer output initial value can be set by the timer output initial value bit (Tn0CR1/Tn1CR1:SO). When the timer stops operating, the timer output bit (TMCRn:TO1/TO0) holds the last value. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 177

Figure 11.11-2 Operation Diagram of PWC Timer (Example of H-pulse Width Measurement) "H" width Pulse input (Input waveform to PWC pin) Counter value 0xFF Time Cleared by program STA bit Counter operation IR bit BF bit Data transferred from counter to Tn0DR/Tn1DR T0nDR/Tn1DR data register read MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 178: Operation Of Input Capture Function

Tn1CR1:IF) is set to "1". The interrupt service routine can therefore be used to count the number of overflows. In addition, the timer output is inverted due to the overflow. The timer output initial value can be set by the timer output initial value bit (Tn0CR1/Tn1CR1:SO). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 179

0xBF 0x9F 0x7F 0x3F Capture value 0xBF 0x7F 0x3F 0x9F in Tn0DR/Tn1DR Rising edge of capture Falling edge of capture Rising edge of Falling edge of capture capture External input Counter clear mode Counter free-run mode MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 180: Operation Of Noise Filter

If the noise filter function is activated, the signal input will be delayed for four machine clock cycles. Figure 11.13-1 Operation of Noise Filter Sampling filter clock External input signal Output filter "H" noise Output filter "L" noise Output filter "H"/"L" noise FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 181

11.14.2 Tn1CR1 8/16-bit composite timer n1 status control register 1 11.14.2 TMCRn 8/16-bit composite timer timer mode control register 11.14.3 Tn0DR 8/16-bit composite timer n0 data register 11.14.4 Tn1DR 8/16-bit composite timer n1 data register 11.14.4 MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 182: Bit Composite Timer Status Control Register 0 (tn0cr0/tn1cr0)

With this bit set to "1", an IF flag interrupt request is output when both the IE bit (Tn0CR1/Tn1CR1:IE) and the IF flag (Tn0CR1/Tn1CR1:IF) are set to "1". bit7 Details Writing "0" Disables the IF flag interrupt. Writing "1" Enables the IF flag interrupt. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 183

Writing "100" MCLK/16 Writing "101" MCLK/32 Writing "110" or F MCRPLL Writing "111" External clock *: The value to be used as the count clock depends on the settings of the SCS[2:0] bits in the SYCC register. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 184

Input capture (falling edge, free-run counter) Writing "1100" Input capture (both edges, free-run counter) Writing "1101" Input capture (rising edge, counter clear) Writing "1110" Input capture (falling edge, counter clear) Writing "1111" Input capture (both edges, counter clear) FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 185: Bit Composite Timer Status Control Register 1 (tn0cr1/tn1cr1)

• Before setting this bit to "1", set the count clock select bits (Tn0CR0/Tn1CR0:C[2:0]), timer operation select bits (Tn0CR0/Tn1CR0:F[3:0]), timer output initial value bit (Tn0CR1/Tn1CR1:SO), 16-bit mode enable bit (TMCRn:MOD), and filter function select bits (TMCRn:FEn1, FEn0). bit7 Details Writing "0" Stops the timer operation. Writing "1" Enables the timer operation. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 186

Indicates that the pulse width measurement has been completed or no edge has been detected. Reading "1" Indicates that the pulse width measurement has been completed or an edge has been detected. Writing "0" Clears this flag. Writing "1" Has no effect on operation. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 187

Reading "0" Indicates that neither timer reload nor overflow has occurred. Reading "1" Indicates that the a timer reload or an overflow has occurred. Writing "0" Clears this flag. Writing "1" Has no effect on operation. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 188

Writing "0" to this bit disables outputting the timer value (TMCRn:TO1/TO0) to the external pin. In this case, the external pin serves as a general-purpose port. Writing "1"to this bit enables outputting the timer value to the external pin. bit0 Details Writing "0" Disables timer output. Writing "1" Enables timer output. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 189: Bit Composite Timer Timer Mode Control Register (tmcrn)

When the timer operating mode select bits (Tn0CR0/Tn1CR0:F[3:0]) are modified with the timer stopping operating, this bit indicates the last value of timer operation if the same timer operation has been performed; otherwise it indicates its initial value "0". MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 190

(the filter function does not operate.). bit3:2 Details Writing "00" Disables the filter function. Writing "01" Filters out "H" pulse noise. Writing "10" Filters out "L" pulse noise. Writing "11" Filters out both "H" pulse noise and "L" pulse noise. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 191

(the filter function does not operate.). bit1:0 Details Writing "00" Disables the filter function. Writing "01" Filters out "H" pulse noise. Writing "10" Filters out "L" pulse noise. Writing "11" Filters out both "H" pulse noise and "L" pulse noise. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 192: Bit Composite Timer Data Register (tn0dr/tn1dr)

The current value can be read from this register. In 16-bit operation, write the upper timer data to Tn1DR and lower timer data to Tn0DR, and write or read Tn1DR first and then Tn0DR. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 193

Therefore, do not write data to the register. In 16-bit operation, write the upper timer data to Tn1DR and lower timer data to Tn0DR, and read Tn1DR first and then Tn0DR. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 194

Figure 11.14-1 shows the Tn0DR and Tn1DR registers read from and written to during 16-bit operation. Figure 11.14-1 Read and Write Operations of Tn0DR and Tn1DR Registers during 16-bit Operation Tn0DR Read register buffer Write Read data data Write Tn1DR buffer register Tn1DR Tn0DR Tn1DR Tn0DR write write read read FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 195: Notes On Using 8/16-bit Composite Timer

(see Figure 11.15-1 and Figure 11.15-2). Therefore, the first interval time or the initial external clock count value is incorrect. Always initialize the counter value after the microcontroller is released from stop mode or watch mode. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 196

(STBC register) Wake-up from stop mode by external interrupt Wake-up from sleep mode by interrupt STP bit (STBC register) HO bit *: The PWM timer output maintains the value held before it enters the stop mode. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 197: Chapter 12 External Interrupt Circuit

This chapter describes the functions and operations of the external interrupt circuit. 12.1 Overview 12.2 Configuration 12.3 Channels 12.4 Pin 12.5 Interrupt 12.6 Operations and Setting Procedure Example 12.7 Register 12.8 Notes on Using External Interrupt Circuit MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 198

Therefore, the operating mode of the device can be changed when a signal is input to the external interrupt pin. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 199

(INT) matches the polarity of the edge selected in the interrupt control register (EIC), a corresponding external interrupt request flag bit (EIR) is set to "1". ● External interrupt control register (EIC) This register is used to select an edge, enable or disable interrupt requests, check for interrupt requests, etc. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 200: Channels

External interrupt input ch. n+2 INTn+3 External interrupt input ch. n+3 The number of external interrupt circuit units varies among products. For the number of external interrupt circuit units in an individual product, refer to the device data sheet. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 201

The state of a pin can always be read from the port data register (PDR) when that pin is set as an input port. The value of PDR can be read by using the read-modify-write (RMW) type of instruction. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 202

(EIC:EIE0 or EIE1 = 1) corresponding to that external interrupt request flag bit is enabled, an interrupt request is generated to the interrupt controller. In an interrupt service routine, write "0" to the external interrupt request flag bit corresponding to that interrupt request generated to clear the interrupt request. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 203

Figure 12.6-1 shows the operations for setting the INTn pin as an external interrupt input. Figure 12.6-1 Operations of External Interrupt Input waveform to INTn pin Interrupt request flag bit cleared by program EIR0 bit EIE0 bit SL01 bit SL00 bit No edge Rising edge Falling edge Both edges detection MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 204

An external interrupt input port shares the same pin with a general-purpose I/O port. Therefore, when using the pin as an external interrupt input port, set the bit in the port direction register (DDR) corresponding to that pin to "0" (input). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 205

CHAPTER 12 EXTERNAL INTERRUPT CIRCUIT MB95630H Series 12.7 Register 12.7 Register This section describes the register of the external interrupt circuit. Table 12.7-1 List of External Interrupt Circuit Register Register Register name Reference abbreviation External interrupt control register 12.7.1 MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 206: External Interrupt Control Register (eic)

The status of the external interrupt pin can be read directly from the port data register, regardless of the status of the interrupt request enable bit. bit4 Details Writing "0" Disables outputting the interrupt request. Writing "1" Enables outputting the interrupt request. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 207

The status of the external interrupt pin can be read directly from the port data register, regardless of the status of the interrupt request enable bit. bit0 Details Writing "0" Disables outputting the interrupt request. Writing "1" Enables outputting the interrupt request. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 208: Notes On Using External Interrupt Circuit

• The device cannot wake up from the interrupt service routine if the external interrupt request flag bit is "1" and the interrupt request enable bit is enabled. In the interrupt service routine, always clear the external interrupt request flag bit. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 209: Chapter 13 Interrupt Pin Selection Circuit

CHAPTER 13 INTERRUPT PIN SELECTION CIRCUIT This chapter describes the functions and operations of the interrupt pin selection circuit. 13.1 Overview 13.2 Configuration 13.3 Pins 13.4 Operation 13.5 Register 13.6 Notes on Using Interrupt Pin Selection Circuit MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 210

INT00 (ch. 0) input of external interrupt. This enables the input signals to the peripheral function pins to also serve as external interrupt pins. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 211

• Selection circuit This circuit outputs the input from the pin selected by the WICR register to the INT00 input of the external interrupt circuit (ch. 0). MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 212

Table 13.3-1 Correspondence between Peripheral Functions and Peripheral Input Pins Peripheral input pin name Peripheral functions name 8/16-bit composite timer (event input) INT00 Interrupt pin selection circuit TRG1 16-bit PPG timer (trigger input) UCK0 UART/SIO (clock input/output) UART/SIO (data input) FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 213: Operation

- When a reset is released, the WICR register is initialized to "0x40" and the INT00 bit is selected as the only available interrupt pin. To use any pins other than the INT00 pin as external interrupt pins, modify the settings of this register before enabling the operation of the external interrupt circuit. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 214

13.5 Register 13.5 Register This section describes the register of the interrupt pin selection circuit. Table 13.5-1 List of External Interrupt Circuit Register Register Register name Reference abbreviation WICR Interrupt pin selection circuit control register 13.5.1 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 215: Interrupt Pin Selection Circuit Control Register (wicr)

INT00 (ch. 0) operation is enabled in the external interrupt circuit. bit3 Details Writing "0" Deselects the EC1 pin as an interrupt input pin. Writing "1" Selects the EC1 pin as an interrupt input pin. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 216

The device wakes up from the standby mode when a valid edge pulse is input to the selected pin. For detail of the standby mode, see "3.5 Operations in Low Power Consumption Mode (Standby Mode)". FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 217

INT00 (ch. 0) of the external interrupt circuit is enabled (the values other than "0b00" are written to the SL0[1:0] bits in the EIC register of the external interrupt circuit.), the selected pins will remain enabled to perform input so as to accept interrupts even in standby mode. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 218: Notes On Using Interrupt Pin Selection Circuit

INT00 (ch. 0) of the external interrupt circuit is treated as "H" if a signal input to one of the selected interrupt pins is "H" (It becomes "OR" of the signals input to the selected pins). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 219: Chapter 14 Lin-uart

This chapter describes the functions and operations of the LIN-UART. 14.1 Overview 14.2 Configuration 14.3 Pins 14.4 Interrupts 14.5 LIN-UART Baud Rate 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example 14.7 Registers 14.8 Notes on Using LIN-UART MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 220

• Detection of LIN synch field start/stop edges connected to the 8/16-bit composite timer Continuous output to the SCK pin enabled for synchronous communication using the Synchronous serial clock start/stop bits Special synchronous clock mode for delaying the clock (used in Serial Peripheral Clock delay option Interface (SPI)) FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 221

Synchronous (Normal mode) Asynchronous (LIN mode) • Operating mode 1 supports both master and slave operation for the multiprocessor mode. • The communication format of operating mode 3 is fixed: 8-bit data, no parity, stop bit 1, LSB-first. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 222

• Bus idle detection circuit • LIN-UART serial control register (SCR) • LIN-UART serial mode register (SMR) • LIN-UART serial status register (SSR) • LIN-UART extended status control register (ESCR) • LIN-UART extended communication control register (ECCR) FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 223: Reload Counter

15-bit register for reload values; it generates the transmit/receive clock from the external or internal clock. The count value in the transmit reload counter is read from the baud rate generator1, 0 (BGR1 and BGR0). MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 224

The circuit stops operating in synchronous mode. ● Interrupt generation circuit This circuit controls all interrupt sources. An interrupt is generated immediately provided that the corresponding interrupt enable bit has been set. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 225

• Enabling/disabling output to the clock pin ● LIN-UART serial status register (SSR) Its operating functions are as follows: • Checking transmission/reception or error status • Selecting the transfer direction (LSB-first or MSB-first) • Enabling/disabling receive interrupts • Enabling/disabling transmit interrupts MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 226

• LIN synch break generation ■ Input Clock The LIN-UART uses a machine clock or an input signal from the SCK pin as an input clock. The input clock is used as the transmission/reception clock source of the LIN-UART. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 227

(SMR:SOE = 1) Set to the input port when this pin is used for clock input. (DDR:corresponding bit = 0) Serial clock input/output Enable output when this pin is used as an clock output pin. (SMR:SCKE = 1) MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 228

With RDRF = 1, the next serial data is received while the CPU has not read the RDR register. (ORE = 1). Framing error A stop bit reception error occurs (FRE = 1). Parity error A parity detection error occurs (PE = 1). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 229

Since the initial value of the TDRE bit is "1" after a hardware reset/software reset, if the TIE bit is set to "1" after a hardware reset/software reset, an interrupt is generated immediately. The TDRE bit is cleared only by writing data to the LIN-UART transmit data register (TDR). MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 230

Stop bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Data = 0x55 Internal signal (LSYN) 8/16-bit Capture value 1 Capture value 2 composite timer Difference in count values = Capture value 2 - Capture Value 1 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 231: Timing Of Receive Interrupt Generation And Flag Set

One reception operation uses 7-bit data, a parity bit (parity bit = "even parity" or "odd parity") and one stop bit. The other uses 8-bit data, no parity bit and one stop bit. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 232

CHAPTER 14 LIN-UART MB95630H Series 14.4 Interrupts Figure 14.4-3 ORE Flag Set Timing Received data ST 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 SP RDRF FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 233: Timing Of Transmit Interrupt Generation And Flag Set

8-bit data, a parity bit ("even parity" or "odd parity") and one stop bit. No parity bit is transmitted in operating mode 3, or in operating mode 2 with SSM = 0. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 234

TDRE bit can be cleared only by writing new data to the LIN-UART transmit data register (TDR). For interrupt request numbers and vector table addresses of respective peripheral functions, refer to "■ INTERRUPT SOURCE TABLE" in the device data sheet. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 235: Lin-uart Baud Rate

(slave operation in operating mode 2 (synchronous) (ECCR:MS = 1)). It is used in synchronous mode (serial clock reception side). As for clock source settings, select the external clock and its direct use (SMR:EXT = 1, OTO = 1). MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 236

Reset Counter value: T (External clock Txc = v/2? input) Transmit clock Internal data bus BGR7 BGR14 BGR6 BGR13 BGR0 BGR5 BGR1 BGR12 BGR4 register register register BGR11 REST BGR3 BGR10 BGR2 BGR9 BGR1 BGR8 BGR0 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 237: Baud Rate Setting

The reload counter stops if the reload value is set to "0". Therefore, set the smallest reload value to "1". For transmission/reception in asynchronous mode, since five times of oversampling have to be done before the reception value is determined, set the reload value to at least "4". MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 238

< 0.01 13541 < 0.01 13332 < 0.01 16666 < 0.01 26666 < 0.01 27082 < 0.01 26666 < 0.01 53332 < 0.01 54166 < 0.01 The unit of frequency deviation is %. MCLK represents machine clock. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 239

LIN-UART. Therefore, if the external clock becomes not divisible because its cycle is faster than half the cycle of the internal clock, the external clock signal becomes unstable. For the value of the SCK clock, refer to the data sheet of this microcontroller. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 240

Figure 14.5-2 Operation of Dedicated Baud Rate Generator (Reload Counter) Transmit/receive clock Falling at (V+1)/2 Reload counter Reload counter value Note: The falling edge of the serial clock signal is generated after the reload value divided by 2 [(V+1)/2] is counted. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 241: Reload Counter

If the REST bit in LIN-UART serial mode register (SMR) is set to "1", the two reload counters restart at the next clock cycle. This function enables the transmit reload counter to be used as a simple timer. Figure 14.5-3 shows an example of using this function (when the reload value is 100). MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 242

Although the counter value is temporarily cleared to "0x00" by the LIN-UART reset (writing "1" to SMR:UPCL), the reload counter restarts since the reload value is kept. If the restart setting is used (writing "1" to SMR:REST), the reload counter restarts without the counter value being cleared to "0x00". FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 243: Operations Of Lin-uart And Lin-uart Setting Procedure Example

• In operating mode 3, the communication format is fixed at "8-bit data, no parity bit, one stop bit, LSB-first". • If the operating mode is changed, all transmission operations and reception operations are canceled, and the LIN-UART waits for the next transmission/reception. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 244

5. Set the baud rate generators 1, 0. (BGR1,BGR0) *: For details of the interrupt level setting register (ILR), refer to "CHAPTER 5 INTERRUPTS" in this hardware manual and "■ INTERRUPT SOURCE TABLE" in the device data sheet. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 245: Operations In Asynchronous Mode (operating Mode 0, 1)

(d = Number of data bits [7 or 8], p = parity [0 or 1], s = Number of stop bits [1 or 2]) Figure 14.6-1 shows the transmit/receive data format in asynchronous mode (operating mode 0, MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 246

P : Parity bit : Address/data bit Note: When the BDS bit in the LIN-UART serial status register (SSR) is set to "1" (MSB-first), the bits are processed in the following order: D7, D6, ... D1, D0 (P). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 247

(SSR:RDRF) is set to "1" and no error has occurred (SSR:PE, ORE, FRE = 0). ● Input clock Use the internal clock or the external clock. For the baud rate, select the baud rate generator (SMR:EXT = 0 or 1, OTO = 0). MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 248

ST: Start bit, SP: Stop bit, Parity used (PEN = 1) Note: In operating mode 1, the parity cannot be used. ● Data signaling NRZ data format. ● Data bit transfer method The data bit transfer method can be LSB-first transfer or MSB-first transfer. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 249: Operations In Synchronous Mode (operating Mode 2)

Data frame ● Start/stop bits When the SSM bit in the LIN-UART extended communication control register (ECCR) is "1", the start and stop bits are added to the data format as they are in asynchronous mode. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 250

When the SCES bit in the LIN-UART extended status register (ESCR) is "1", the LIN-UART clock is inverted, and receive data is sampled at the falling edge of the LIN-UART clock. At that time, the value of the serial data must become valid at the edge of the LIN-UART clock. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 251

- For SSM = 1: PEN : "1": Adds/detects parity bit, "0": Not use parity bit : "1": Even parity, "0": Odd parity SBL : "1": Stop bit length 2, "0": Stop bit length 1 MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 252

To receive data only, disable the serial output (SMR:SOE = 0), and then write dummy data to the TDR register. Enabling continuous clock output and the start/stop bits enables bi-directional communication as that in asynchronous mode. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 253: Operations Of Lin Function (operating Mode 3)

In addition, enable the 8/16-bit composite timer interrupt and make the 8/16-bit composite timer detect both edges. The time at which the input signal input to the 8/16-bit composite timer is eight times the baud rate. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 254

LIN break interrupt (if the following communication format is used: 8-bit data, no parity, one stop bit.), set the RXE to "0" when using the LIN break. The LIN synch break detection functions only in operating mode 3. Figure 14.6-8 shows the LIN-UART operation in LIN slave mode. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 255

IRQ clear: input capture of 8/16-bit composite timer count starts IRQ (8/16-bit composite timer) IRQ clear: Baud rate calculated and set LBIE disabled Reception enabled Falling edge of start bit 1 byte of reception data saved to RDR RDR read by CPU MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 256: Serial Pin Direct Access

SIOP bit holds a previous value. While the value of the SIN pin is read by normal read, the value of the SOT pin is read from the SIOP bit by the read-modify-write (RMW) type of instruction. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 257: Bidirectional Communication Function (normal Mode)

When using bidirectional communication, connect two CPUs as shown in Figure 14.6-11. Figure 14.6-11 Example of Connection for Bidirectional Communication in LIN-UART Operating Mode 2 Output Input CPU1 CPU2 (Serial clock transmit side) (Serial clock receive side) MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 258

(0 or 2) (same as that of the master) Data transmission Communicate with 1-byte data set in TDR Data received? Data received? Read and process received data Data transmission Read and process received Transmit 1-byte data data (ANS) FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 259: Master/slave Mode Communication Function (multiprocessor Mode)

Figure 14.6-14 Connection Example of LIN-UART Master/Slave Mode Communication Master CPU Slave CPU #1 Slave CPU #0 ● Function selection In master/slave mode communication, select the operating mode and the data transfer method as shown in Figure 14.6-14. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 260

A slave CPU uses a program to check address data, and communicates with the master CPU when the address data matches the address assigned to that slave CPU. Figure 14.6-15 is a flow chart showing master/slave mode communication (multiprocessor mode). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 261

Transmit address to slave AD bit = 1 Slave address matches address data Set AD bit to "0" Communicate with master Communicate with slave Terminate Terminate communication? communication? Communicate with another slave Disable transmission/ reception MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 262: Lin Communication Function

Figure 14.6-17 shows an example of communication in a LIN bus system. The LIN-UART can operate as a LIN master or a LIN slave. Figure 14.6-17 Example of LIN Bus System Communication LIN bus LIN master Transceiver Transceiver LIN slave FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 263: Examples Of Lin-uart Lin Communication Flow Chart (operating Mode 3)

* 2: - If the FRE or ORE flag is set to "1", write "1" to the SCR:CRE bit to clear the error flag. - If the ESCR:LBD bit is set to "1", execute the LIN-UART reset. Note: Deal properly with any error detected in a process. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 264

* 2: - If the FRE or ORE flag is set to "1", write "1" to the SCR:CRE bit to clear the error flag. - If the ESCR:LBD bit is set to "1", execute the LIN-UART reset. Note: Deal properly with any error detected in a process. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 265

14.7.4 LIN-UART transmit data register 14.7.4 ESCR LIN-UART extended status control register 14.7.5 ECCR LIN-UART extended communication control register 14.7.6 BGR1 LIN-UART baud rate generator register 1 14.7.7 BGR0 LIN-UART baud rate generator register 0 14.7.7 MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 266: Lin-uart Serial Control Register (scr)

This bit is fixed at "0" in operating mode 3 (LIN). bit5 Details Writing "0" 1 bit Writing "1" 2 bits Note: At reception, only a framing error for the bit length of the stop bit is always detected. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 267

Disables data frame transmission. Writing "1" Enables data frame transmission. Note: When data frame transmission is disabled (TXE = 0) while it is in progress, the transmission halts immediately. In this case, the integrity of data is not guaranteed. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 268: Lin-uart Serial Mode Register (smr)

Selects the external serial clock source. [bit3] REST: Reload counter restart bit This bit restarts the reload counter. bit3 Details Read access The read value is always "0". Writing "0" Has no effect on operation. Writing "1" Restarts the reload counter. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 269

I/O port sharing the same pin with SOT. bit0 Details Writing "0" Makes the SOT pin function as a general-purpose I/O port. Writing "1" Makes the SOT pin function as the LIN-UART serial data output pin. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 270: Lin-uart Serial Status Register (ssr)

When this flag is set, the data in the LIN-UART receive data register (RDR) is invalid. bit5 Details Reading "0" Indicates that no framing error has been detected. Reading "1" Indicates that a framing error has been detected. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 271

This bit enables or disables the transmit interrupt request output to the interrupt controller. When both the TIE bit and the TDRE bit are "1", a transmit interrupt request is output. bit0 Details Writing "0" Disables the transmit interrupt. Writing "1" Enables the transmit interrupt. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 272: Lin-uart Receive Data Register/lin-uart Transmit Data Register (rdr/tdr)

If the transmit data register empty flag bit (SSR:TDRE) is "1", the next transmit data can be written to TDR. If the transmit interrupt has been enabled, a transmit interrupt is generated. Write the next transmit data to TDR after a transmit interrupt or when the transmit data register empty flag bit (SSR:TDRE) is "1". FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 273

Since both registers are located at the same address, the write value and the read value are different. Thus, the read-modify-write (RMW) type of instruction, such as the INC instruction and the DEC instruction, cannot be used. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 274: Lin-uart Extended Status Control Register (escr)

Writing "0" Clears this bit. Writing "1" Has no effect on operation. Note: To detect a LIN synch break, enable the LIN synch break detection interrupt (LBIE = 1), and then disable the reception (SCR:RXE = 0). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 275

SIOP bit is held.) It writes "0" or "1" to the SOT pin. It returns the value of the SIN pin. It reads the value of the SOT pin and writes "0" or "1" to the SOT pin. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 276

Details (only for operating mode 2) Writing "0" Selects the rising edge of the clock as the sampling edge (normal). Writing "1" Selects the falling edge of the clock as the sampling edge (inverted clock). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 277: Lin-uart Extended Communication Control Register (eccr)

Selects the reception side (external serial clock reception). Note: When the reception side is selected, select the external clock as the clock source and enable the external clock input (SMR:SCKE = 0, EXT = 1, OTO = 1). MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 278

If there is no transmission on the SOT pin, this bit is "1". Do not use this bit when SSM = 0 in operating mode 2. bit0 Details Reading "0" Indicates that transmission is in progress. Reading "1" Indicates that there is no transmission operation. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 279: Lin-uart Baud Rate Generator Registers 1, 0 (bgr1, Bgr0)

BGR0 can be accessed by byte access and word access. Writing a reload value to the LIN-UART baud rate generator registers causes the reload counter to start counting. Write values to the BGR1 register or the BGR0 register only when the LIN-UART has stopped operating. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 280: Notes On Using Lin-uart

In the case of not following the above procedure to modify operating settings, proper operations of this device cannot be guaranteed. Though the transmission bit length of the LIN break field is variable, the detection bit length of the LIN break field is fixed at 11 bits. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 281

The above problem can also be prevented by always using byte access to write values to the SCR register. ● LIN-UART software reset Execute the LIN-UART software reset (SMR:UPCL = 1) when the TXE bit in the LIN-UART serial control register (SCR) is "0". MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 282

(RXE = 1 0 1). Therefore, the falling edge of the serial data input (SIN) is detected, the start bit is recognized when "L" is detected at the reception sampling point, and the reception is started (See "When reception is temporarily disabled (RXE = 1 0 1)" in Figure 14.8-1). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 283

When reception is temporarily disabled (RXE = 1 Reception is reset: Falling edge is Error is cleared Waitng for falling edge Framing error next start bit occurs edge No further errors Reception is ongoing regardress of no falling edge MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 284

CHAPTER 14 LIN-UART MB95630H Series 14.8 Notes on Using LIN-UART FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 285: Chapter 15 8/10-bit A/d Converter

8/10-BIT A/D CONVERTER This chapter describes the functions and operations of the 8/10-bit A/D converter. 15.1 Overview 15.2 Configuration 15.3 Pin 15.4 Interrupt 15.5 Operations and Setting Procedure Example 15.6 Registers 15.7 Notes on Using 8/10-bit A/D Converter MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 286

• The completion of conversion can be determined according to the ADI bit in the ADC1 register. To activate the A/D conversion function, use one of the following methods. • Activation using the AD bit in the ADC1 register • Continuous activation using the 8/16-bit composite timer output TO00 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 287

8/10-bit A/D converter data register(upper/lower) (ADDH/ADDL) ANS3 ANS2 ANS1 ANS0 ADMV Reserved 8/10-bit A/D converter control register 1 (ADC1) ● Clock selector This selects the A/D conversion clock with continuous activation having been enabled (ADC2:EXT = 1). MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 288

This register is used to select an input clock, enable and disable interrupts and control different functions of the A/D converter. ■ Input Clock The 8/10-bit A/D converter uses an output clock from the prescaler as the input clock (operating clock). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 289

(DDR) corresponding to that pin, and the value corresponding to that pin to the analog input pin select bits (ADC1:ANS[3:0]). A pin not used as an analog input pin can be used as a general-purpose I/O port even when the 8/10-bit A/D converter is in use. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 290

ADIE bit. The CPU cannot return from interrupt processing if the interrupt request flag bit (ADC1:ADI) is "1" with interrupt requests having been enabled (ADC2:ADIE = 1). Always clear the ADI bit in the interrupt service routine. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 291

× : Unused bit 0 : Set to "0" 1 : Set to "1" When the A/D conversion function is activated, A/D conversion starts. In addition, the A/D conversion function can be re-activated even during conversion. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 292

(ADC2:EXT = 0) before changing the analog input pin. • A reset, or the start of the stop mode or watch mode causes the A/D converter to stop and the ADMV bit to be cleared to "0". FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 293

"■ INTERRUPT SOURCE TABLE" in the device data sheet. ● Interrupt processing 1. Clear the interrupt request flag to "0". (ADC1:ADI = 0) 2. Read converted values. (ADDH, ADDL) 3. Activate the A/D conversion function. (ADC1:AD = 1) MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 294

Register name Reference abbreviation ADC1 8/10-bit A/D converter control register 1 15.6.1 ADC2 8/10-bit A/D converter control register 2 15.6.2 ADDH 8/10-bit A/D converter data register (upper) 15.6.3 ADDL 8/10-bit A/D converter data register (lower) 15.6.3 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 295: Bit A/d Converter Control Register 1 (adc1)

• Do not write to ANS[3:0] any value other than those listed in the table above. • When the ADMV bit is "1", do not modify these bits. Pins not used as analog input pins can be used as general- purpose I/O ports. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 296

Has no effect on operation. Writing "1" Starts the A/D conversion function. Note: Writing "0" to this bit cannot stop the operation of the A/D conversion function. The read value of this bit is always "0". FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 297: Bit A/d Converter Control Register 2 (adc2)

Writing "0" Selects not using any external start signal to start the A/D conversion function. Selects the 8/16-bit composite timer ch. 0 output pin (TO00) as the pin used to start the A/D Writing "1" conversion function. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 298

Modify these bits according to operating conditions (voltage and frequency). Details bit1:0 (MCLK: machine clock) Writing "00" 1 MCLK Writing "01" MCLK/2 Writing "10" MCLK/4 Writing "11" MCLK/8 Note: Modify these bits only when the A/D converter has stopped operating. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 299: Bit A/d Converter Data Register (upper/lower) (addh/addl)

After A/D conversion is completed and before the next A/D conversion is completed, read A/D data registers (conversion results), and clear the interrupt request flag bit (ADI) in the ADC1 register. During A/D conversion, the values of the ADDH and ADDL registers are results of the last A/D conversion. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 300: Notes On Using 8/10-bit A/d Converter

Compare time = CKIN 10 (fixed value) + MCLK A/D converter startup time: minimum = MCLK + MCLK maximum = MCLK + CKIN Conversion time = A/D converter startup time + sampling time + compare time FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 301

A/D conversion starts. • When setting the A/D converter in software, ensure that the settings satisfy the specifications of "sampling time" and "compare time" of the A/D converter mentioned in the device data sheet. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 302

CHAPTER 15 8/10-BIT A/D CONVERTER MB95630H Series 15.7 Notes on Using 8/10-bit A/D Converter FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 303: Chapter 16 Low-voltage Detection Reset Circuit

CHAPTER 16 LOW-VOLTAGE DETECTION RESET CIRCUIT This chapter describes the function and operation of the low-voltage detection reset circuit. 16.1 Overview 16.2 Configuration 16.3 Pins 16.4 Operation 16.5 Register MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 304

At power-on, the lowest reset threshold voltage is selected in the LVDR register. The circuit is only available on certain products. Check the availability of the circuit in the device data sheet. Refer also to the device data sheet for details of the electrical characteristics. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 305

■ Block Diagram of Low-voltage Detection Reset Circuit Figure 16.2-1 Block Diagram of Low-voltage Detection Reset Circuit 0xAA 0x5A Reset signal 0x55 N-ch Other Vref values LVRS7 LVRS6 LVRS5 LVRS4 LVRS3 LVRS2 LVRS1 LVRS0 LVD reset voltage selection ID register (LVDR) MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 306

The low-voltage detection reset circuit monitors the voltage of this pin. ● V This is the GND pin serving as the reference for voltage detection. ● RST pin The low-voltage detection reset signal is output inside the microcontroller and to this pin. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 307

Reset signal A: Delay B: Oscillation stabilization wait time ■ Operation in Standby Mode The low-voltage detection reset circuit keeps operating even in standby mode (stop mode, sleep mode, subclock mode and watch mode). MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 308

16.5 Register 16.5 Register This section describes the register of low-voltage detection reset circuit. Table 16.5-1 List of Low-voltage Detection Reset Circuit Register Register Register name Reference abbreviation LVDR LVD reset voltage selection ID register 16.5.1 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 309: Lvd Reset Voltage Selection Id Register (lvdr)

Writing a value other than the above 2.6 V 2.7 V Note: The reset of the low-voltage detection reset circuit has no effect on the reset threshold voltage settings as the reset cannot clear this register. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 310

CHAPTER 16 LOW-VOLTAGE DETECTION RESET CIRCUIT MB95630H Series 16.5 Register FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 311: Chapter 17 Clock Supervisor Counter

CHAPTER 17 CLOCK SUPERVISOR COUNTER This chapter describes the functions and operations of the clock supervisor counter. 17.1 Overview 17.2 Configuration 17.3 Operations 17.4 Registers 17.5 Notes on Using Clock Supervisor Counter MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 312

Otherwise, it cannot detect the abnormal state of the external clock correctly and will hang up if the external clock stops. See "CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER" for the hardware watchdog timer (running in standby mode). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 313

Time-base timer output Output Selector 8-bit Counter Main oscillation clock Counter 1st: counting starts Source 2nd: counting stops Clock Selector Sub-oscillation clock Control Circuit Counter enabled Clock Monitoring Control Register (CMCR) Clock Monitoring Data Register (CMDR) Internal Bus MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 314

This block is used to select the counter enable period from eight different time-base timer intervals. ● Counter source clock selector This block is used to select the counter source clock from the main oscillation clock and the suboscillation clock. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 315

● Clock Supervisor Counter Operation 2 The CMDR register is cleared when the CMCEN bit changes from "0" to "1". Figure 17.3-2 Clock Supervisor Counter Operation 2 Selected time-base timer interval Main/Sub-oscillation clock CMCEN Clear Internal counter CMDR register MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 316

The counter is cleared to "0" by the software if the CMCEN is set to "0" while the counter is operating. Figure 17.3-5 Clock Supervisor Counter Operation 5 Selected time-base timer interval Main/Sub-oscillation clock Software setting CMCEN Internal counter CMDR register FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 317

2613 10449 41796 167184 1253 5018 20077 80312 321253 1307 5225 20898 83592 334368 2038 8155 32626 130508 522038 32.5 2123 8490 33960 135837 543347 : Recommended setting : The counter value becomes "0" or "255". MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 318

Time-base Timer Interval > ----------------------- 1.05 4.3 ms TBC[3:0] = 0b0110 (2 Notes: • See "7.1 Overview" for time-base timer interval settings. • See "3.3.3 Oscillation Stabilization Wait Time Setting Register (WATR)" for main/ sub-oscillation stabilization time settings. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 319

“1”, that means the external clock is dead or the external clock frequency is Main clock oscillation stabilization bit — SYCC2:MRDY abnormal.) Subclock oscillation stabilization bit — SYCC2:SRDY MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 320

Registers This section describes the registers of the clock supervisor counter. Table 17.4-1 List of Clock Supervisor Counter Registers Register Register name Reference abbreviation CMDR Clock monitoring data register 17.4.1 CMCR Clock monitoring control register 17.4.2 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 321: Clock Monitoring Data Register (cmdr)

• After the external clock stops, the falling edge of the selected time-base timer clock is detected twice. (See Figure 17.5-2.) Note: The value of this register is "0b00000000" as long as the counter is operating (CMCR:CMCEN = 1). MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 322: Clock Monitoring Control Register (cmcr)

The first rising edge of the interval selected enables the counter operation and the second rising edge of the same output disables the counter operation. Details bit3:1 : main CR clock) Writing "000" Writing "001" Writing "010" Writing "011" Writing "100" Writing "101" Writing "110" Writing "111" FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 323

Disables the counter operation. Writing "1" Enables the counter operation. Notes: • Do not modify the CMCSEL bit when the CMCEN bit is "1". • Do not modify the TBTSEL[2:0] bits when the CMCEN bit is "1". MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 324: Notes On Using Clock Supervisor Counter

TBTSEL[2:0] DIV[1:0] 010 to 111 (clock gear setting) to 2 ❍ ❍ ❍ 00 (1 1/F ❍ ❍ 01 (4 1/F ❍ ❍ 10 (8 1/F ❍ 11 (16 1/F ❍ : Recommended x : Prohibited FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 325

The counter is cleared at the same falling edge. Figure 17.5-2 Clock Supervisor Counter Operation 2 Selected time-base timer interval Main/Sub-oscillation clock CMCEN Internal counter CMDR register MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 326

CHAPTER 17 CLOCK SUPERVISOR COUNTER MB95630H Series 17.5 Notes on Using Clock Supervisor Counter FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 327: Chapter 18 8/16-bit Ppg

8/16-BIT PPG This chapter describes the functions and operations of the 8/16-bit PPG. 18.1 Overview 18.2 Configuration 18.3 Channel 18.4 Pins 18.5 Interrupt 18.6 Operations and Setting Procedure Example 18.7 Registers 18.8 Notes on Using 8/16-bit PPG MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 328

In this operation, a variable-cycle pulse waveform is output in any duty ratio. The unit can also be used as a D/A converter in conjunction with an external circuit. ● Output inversion mode This mode can invert the PPG output value. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 329

MCLK/16 detection LOAD circuit CL K MCLK/32 or F or F MCRPLL or F or F 8-bit downcounter MCRPLL (PPG timer n1) STOP REV01 PEN01 PPGn1 Edge START BORROW detection PIE1 PUF1 POEN1 POEN1 IRQXX MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 330

● 8/16-bit PPG output inversion register An initial level also includes the output of 8/16-bit PPG timer and it is reversed. ■ Input Clock The 8/16-bit PPG uses the output clock from the prescaler as its input clock (count clock). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 331

8/16-bit PPG timer n0 cycle setup buffer register PDSn1 8/16-bit PPG timer n1 duty setup buffer register PDSn0 8/16-bit PPG timer n0 duty setup buffer register PPGS 8/16-bit PPG start register REVC 8/16-bit PPG output inversion register MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 332

PPGn0, PPGn1: A PPG waveform is output to these pins. The PPG waveform can be output by enabling the output by the 8/16-bit PPG timer n1/n0 control registers (PCn0: POEN0 = 1, PCn1: POEN1 = 1). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 333

(PUF) in the 8/16-bit PPG timer n0/n1 control register (PC) to "1". When the interrupt request enable bit is enabled (PIE = 1), an interrupt request is output to the interrupt controller. In 16-bit PPG mode, the 8/16-bit PPG timer n0 control register (PCn0) is available. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 334

Operations and Setting Procedure Example This section describes the operations of the 8/16-bit PPG. The 8/16-bit PPG has the following three operating modes: • 8-bit PPG independent mode • 8-bit prescaler + 8-bit PPG mode • 16-bit PPG mode FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 335: Bit Ppg Independent Mode

After "H" which is the value of duty setting is output, "L" is output to the PPG output. If, however, the PPG output level reverse bit is set to "1", the PPG output is set and reset inversely from the above process. Figure 18.6-2 shows the operation of the 8-bit PPG independent mode. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 336

When the PDS register is set to "0x02" with the PPS register set to "0x04", the PPG output is set at a duty ratio of 50% (half the value of the PPS register is set to the PDS register). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 337: Bit Prescaler + 8-bit Ppg Mode

PPGn1 output is set to "L". If the output level reverse signal (REV01) is "0", the polarity remains the same. If it is "1", the polarity is MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 338

(2) = m1 n0: PDSn0 register value The value changes depending on the (3) = (1) m1: PPSn1 register value PPGn1 output (ch. n) waveform and the (4) = (1) n1: PDSn1 register value PEN00 start timing. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 339: Bit Ppg Mode

• When the values of the downcounters match the values in the 8/16-bit PPG timer duty setup buffer registers (both the value in PDSn1 for PPG timer n1 and the value in PDSn0 for PPG timer n0), the PPGn0 pin is set to "H" synchronizing with the count clock. After "H" which MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 340

(Normal polarity) (Reverse polarity) T: Count clock cycle (1) = n m: PPSn1 & PPSn0 (2) = m n: PDSn1 & PDSn0 : The value changes depending on the count clock selected and the start timing. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 341

*: For details of the interrupt level setting register (ILR), refer to "CHAPTER 5 INTERRUPTS" in this hardware manual and "■ INTERRUPT SOURCE TABLE" in the device data sheet. ● Interrupt processing 1. Process any interrupt. 2. Clear the interrupt request flag. (PCn1:PUF1, PCn0:PUF0) 3. Start the 8/16-bit PPG. (PPGS) MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 342

8/16-bit PPG timer n0 cycle setting buffer register 18.7.3 PDSn1 8/16-bit PPG timer n1 duty setting buffer register 18.7.4 PDSn0 8/16-bit PPG timer n0 duty setting buffer register 18.7.4 PPGS 8/16-bit PPG start register 18.7.5 REVC 8/16-bit PPG output reverse register 18.7.6 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 343: Bit Ppg Timer N1 Control Register (pcn1)

REV01 is output. "L" output is supplied when REV01 is "0".) bit3 Details Writing "0" The PPG timer n1 pin functions as a general-purpose I/O port. Writing "1" The PPG timer n1 pin functions as a PPG output pin. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 344

Writing "110" or F or F MCRPLL Writing "111" or F or F MCRPLL Note: In subclock mode or sub-CR clock mode, since the time-base timer stops operating, setting CKS1[2:0] to "0b110" or "0b111" is prohibited. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 345: Bit Ppg Timer N0 Control Register (pcn0)

Indicates that no counter borrow of PPG timer n0 has been detected. Reading "1" Indicates that a counter borrow of PPG timer n0 has been detected. Writing "0" Clears this bit. Writing "1" Has no effect on operation. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 346

Writing "110" or F or F MCRPLL Writing "111" or F or F MCRPLL Note: In subclock mode or sub-CR clock mode, since the time-base timer stops operating, setting CKS0[2:0] to "0b110" or "0b111" is prohibited. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 347: Bit Ppg Timer N1/n0 Cycle Setup Buffer Register (ppsn1/ppsn0)

• Do not set the cycle to "0x0000" or "0x0001" when using the unit in 16-bit PPG mode. • If the cycle settings are modified during the operation, the modified settings will be effective from the next PPG cycle. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 348: Bit Ppg Timer N1/n0 Duty Setup Buffer Register (pdsn1/pdsn0)

"L" output in the normal polarity (when the output level inversion bit of 8/16-bit PPG output inversion register is "0"). • If the duty settings are modified during operation, the modified value will be effective from the next PPG cycle. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 349: Bit Ppg Start Register (ppgs)

This bit enables or stops the downcounter operation of PPG timer 10 (ch. 1). bit2 Details Writing "0" Stops the downcounter operation of PPG timer 10 (ch. 1). Writing "1" Enables the downcounter operation of PPG timer 10 (ch. 1). MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 350

This bit enables or stops the downcounter operation of PPG timer 00 (ch. 0). bit0 Details Writing "0" Stops the downcounter operation of PPG timer 00 (ch. 0). Writing "1" Enables the downcounter operation of PPG timer 00 (ch. 0). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 351: Bit Ppg Output Reverse Register (revc)

Selects reverse polarity. [bit2] REV10: PPG timer 10 (ch. 1) output level reverse bit This bit selects the output level of PPG timer 10 (ch. 1). bit2 Details Writing "0" Selects normal polarity. Writing "1" Selects reverse polarity. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 352

Selects reverse polarity. [bit0] REV00: PPG timer 00 (ch. 0) output level reverse bit This bit selects the output level of PPG timer 00 (ch. 0). bit0 Details Writing "0" Selects normal polarity. Writing "1" Selects reverse polarity. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 353: Notes On Using 8/16-bit Ppg

A PPG interrupt is generated when the interrupt enable bit (PIE1/PIE0) is set to "1" and the interrupt request flag bit (PUF1/PUF0) in the 8/16-bit PPG timer n1/n0 control register (PCn1/ PCn0) is also set to "1". Always clear the interrupt request flag bit (PUF1/PUF0) to "0" in the interrupt service routine. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 354

CHAPTER 18 8/16-BIT PPG MB95630H Series 18.8 Notes on Using 8/16-bit PPG FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 355: Chapter 19 16-bit Ppg Timer

This chapter describes the functions and operations of the 16-bit PPG timer. 19.1 Overview 19.2 Configuration 19.3 Channel 19.4 Pins 19.5 Interrupts 19.6 Operations and Setting Procedure Example 19.7 Registers 19.8 Notes on Using 16-bit PPG Timer MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 356

- Occurrence of a counter borrow in the 16-bit downcounter (cycle match). - Rising edge of PPG in normal polarity or falling edge of PPG in inverted polarity - Counter borrow, rising edge of PPG in normal polarity, or falling edge of PPG in inverted polarity FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 357

● Count clock selector The clock for the countdown of 16-bit downcounter is selected from eight types of internal count clocks. ● 16 bit downcounter It counts down with the count clock selected with the count clock selector. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 358

● 16-bit PPG status control register (upper/lower) ch. n (PCNTHn/PCNTLn) The operation mode and the operation condition of 16-bit PPG timer are set. ■ Input Clock The 16-bit PPG timer uses the output clock from the prescaler as its input clock (count clock). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 359

16-bit PPG duty setting buffer register (upper) ch. n PDUTLn 16-bit PPG duty setting buffer register (lower) ch. n PCNTHn 16-bit PPG status control register (upper) ch. n PCNTLn 16-bit PPG status control register (lower) ch. n MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 360

PPGn: A PPG waveform is output to this pin. The PPG waveform can be output by using the 16-bit PPG status control register to enable output (PCNTLn:POEN=1). ● TRGn pin TRGn:Used to start the 16-bit PPG timer by the hardware trigger. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 361

When the IRQF bit in the 16-bit PPG status control register (PCNTLn) is set to "1" and interrupt requests are enabled (PCNTLn:IREN = 1) in the 16-bit PPG timer, an interrupt request is generated and output to the controller. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 362

Hardware trigger by TRGn pin input : 1 count clock cycle + 3 machine clock cycles The minimum time is as follows. Software trigger : 2 machine clock cycles Hardware trigger by TRGn pin input : 3 machine clock cycles FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 363

Rising edge detected Restarted by trigger Software trigger (Normal polarity) (Inverted polarity) T : Count clock cycle (1)=n T ns m: Value of PCSRH & PCSRL registers (2)=m T ns n : Value of PDUTH & PDUTL registers MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 364

Rising edge detected Trigger restarted Software trigger (Normal polarity) (Inverted polarity) T : Count clock cycle (1)=n T ns m: Value of PCSRH & PCSRL registers (2)=m T ns n : Value of PDUTH & PDUTL registers FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 365

*: For details of the interrupt level setting register (ILR), refer to "CHAPTER 5 INTERRUPTS" in this hardware manual and "■ INTERRUPT SOURCE TABLE" in the device data sheet. ● Interrupt processing 1. Process any interrupt. 2. Clear the interrupt request flag. (PCNTLn:IRQF) MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 366

16-bit PPG duty setting buffer register (upper) ch. n 19.7.3 PDUTLn 16-bit PPG duty setting buffer register (lower) ch. n 19.7.3 PCNTHn 16-bit PPG status control register (upper) ch. n 19.7.4 PCNTLn 16-bit PPG status control register (lower) ch. n 19.7.5 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 367: Bit Ppg Downcounter Register (upper/lower) Ch. N (pdcrhn/pdcrln)

This register is read-only and writing a value to this register has no effect on the operation. Note: If you use the "MOV" instruction and read PDCRLn before PDCRHn, PDCRLn returns the value from the previous valid read operation. Therefore, the value of the 16-bit downcounter cannot be read correctly. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 368: Bit Ppg Cycle Setting Buffer Register (upper/ Lower) Ch. N Pcsrhn/pcsrln)

If the downcounter load occurs after the "MOV" instruction is used to write data to PCSRLn before PCSRHn, the previous valid PCSRHn value and newly written PCSRLn value are loaded to the downcounter. It should be noted that as a result, the correct period cannot be set. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 369: Bit Ppg Duty Setting Buffer Register (upper/lower) Ch. N (pduthn/pdutln)

• When the value set in the duty setting registers is greater than the value in the 16-bit PPG cycle setting buffer registers, the "L" level will always be output if normal polarity is set, and the "H" level will always be output if inverted polarity is set. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 370: Bit Ppg Status Control Register (upper) Ch. N (pcnthn)

This bit selects the operating mode of the 16-bit PPG timer. bit5 Details Writing "0" PWM mode Writing "1" One-shot mode Note: While the 16-bit PPG timer is in operation, modifying the setting of this bit is prohibited. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 371

When the polarity setting is se to "inverted" (PCNTLn:OSEL = 1), the PPGn output is always masked to "H". bit0 Details Writing "0" Disables the PPGn output mask function. Writing "1" Enables the PPGn output mask function. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 372: Bit Ppg Status Control Register (lower) Ch. N (pcntln)

Reading "0" Indicates that no 16-bit PPG timer interrupt has been generated. Reading "1" Indicates that a 16-bit PPG timer interrupt has been generated. Writing "0" Clears this bit. Writing "1" Has no effect on operation. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 373

16-bit downcounter value matches the duty setting register value, and goes to "L" when a downcounter borrow occurs (normal polarity). When "1" is written to this bit, the 16-bit PPG timer output is inverted (inverted polarity). bit0 Details Writing "0" Normal polarity Writing "1" Inverted polarity MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 374: Notes On Using 16-bit Ppg Timer

0b00), never disable the 16-bit PPG timer operation (PCNTHn:CNTE = 0) and enable the software trigger (PCNTHn:STRG = 1) at the same time. Otherwise, even though the 16-bit PPG timer stops operating, the interrupt flag bit may be set by a retrigger. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 375: Chapter 20 16-bit Reload Timer

This chapter describes the functions and operations of the 16-bit reload timer. 20.1 Overview 20.2 Configuration 20.3 Channel 20.4 Pins 20.5 Interrupt 20.6 Operations and Setting Procedure Example 20.7 Registers 20.8 Notes on Using 16-bit Reload Timer MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 376

(rising, falling, or both) specified by the operating mode select bits (MOD[2:0]) is input to the TIn pin. When an external clock is input in regular cycles, the reload timer can also be used as an interval timer. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 377

16-bit reload timer can be used as the interval timer. ● One-shot mode An interrupt is generated when an underflow occurs on the 16-bit downcounter. During counter operation, the TOn pin outputs a square waveform indicating that the counter is currently running. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 378

16-bit reload timer control 16-bit reload timer control CSL2 CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG status register (upper) ch. n (TMCSRHn) status register (lower) ch. n (TMCSRLn) Interrupt request signal Internal bus FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 379

16-bit reload timer as well as indicates the current operation status. ■ Input Clock The 16-bit reload timer uses the output clock from the prescaler or the input signal from the TIn pin as its input clock (count clock). MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 380

TMRHn 16-bit reload timer timer register (upper) ch. n TMRLn 16-bit reload timer timer register (lower) ch. n TMRLRHn 16-bit reload timer reload register (upper) ch. n TMRLRLn 16-bit reload timer reload register (lower) ch. n FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 381

When this pin is used as the 16-bit reload timer output pin, regardless of the setting of port direction register (DDR), enabling 16-bit reload timer output (TMCSRLn:OUTE = 1) automatically makes this pin function as the 16-bit reload timer output pin to output the waveforms. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 382

(lower) ch. n (TMCSRLn) to "1" when an underflow occurs in the 16-bit downcounter ("0x0000" "0xFFFF"). If the underflow interrupt request has been enabled (TMCSRLn:INTE = 1), the interrupt request will be output to the interrupt controller. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 383

: State transition by register access WAIT : WAIT signal (internal signal) : Software trigger bit (TMCSRLn) CNTE : Timer operation enable bit (TMCSRLn) : Underflow generation flag bit (TMCSRLn) RELD : Reload selection bit (TMCSRLn) MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 384

"■ INTERRUPT SOURCE TABLE" in the device data sheet. ● Interrupt processing 1. Clear the underflow interrupt request flag. (TMCSRLn:UF=0) 2. Disable underflow interrupt. (TMCSRLn:INTE = 0) 3. Process any interrupt. 4. Enable underflow interrupt. (TMCSRLn:INTE = 1) FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 385: Internal Clock Mode

(UF) is "1" when the underflow interrupt request enable bit (INTE) is set to "1", an interrupt request is output. The TOn pin can output a toggle waveform that is inverted every time an underflow occurs. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 386

(MOD[2:0]) is being input to the TIn pin. The timer start with the software trigger becomes effective as well as the one with an external trigger. Figure 20.6-5 shows the gate input operation in reload mode. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 387

Figure 20.6-6 Count Operation in One-shot Mode (Software Trigger Operation) Count clock 0000 FFFF 0000 FFFF Counter Reload data Reload data Data load signal UF bit CNTE bit TRG bit TOn pin Wait for start trigger input MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 388

Figure 20.6-8 Count Operation in One-shot Mode (External Gate Input Operation) Count clock 0000 FFFF Counter Reload data Reload data Data load signal UF bit CNTE bit TRG bit TIn pin TOn pin Wait for start trigger input FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 389: Event Count Mode

16-bit counter, and an interrupt request is output if the underflow interrupt enable bit (INTE) is set to "1". The TOn pin can output a toggle waveform that is inverted each time an underflow occurs. Figure 20.6-10 shows the count operation in reload mode. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 390

Figure 20.6-11 Counter Operation in One-shot Mode (Event Count Mode) TIn pin 0000 FFFF 0000 FFFF Counter Reload data Reload data Data load signal UF bit CNTE bit TRG bit TOn pin Wait for start trigger input FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 391

16-bit reload timer timer register (upper) ch. n 20.7.3 TMRLn 16-bit reload timer timer register (lower) ch. n 20.7.3 TMRLRHn 16-bit reload timer reload register (upper) ch. n 20.7.4 TMRLRLn 16-bit reload timer reload register (lower) ch. n 20.7.4 MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 392: Bit Reload Timer Control Status Register (upper) Ch. N (tmcsrhn)

Writing "100" MCLK/16 Writing "101" MCLK/32 Writing "110" or F or F MCRPLL Writing "111" Event count mode External clock *: MCLK: machine clock : main clock : main CR PLL clock MCRPLL : main CR clock FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 393

TIn pin function Valid edge/level Writing "000" External pin input invalid — Writing "001" Rising edge Writing "010" Trigger input Falling edge Writing "011" Both edges Writing "100" Writing "101" Setting prohibited Writing "110" Writing "111" MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 394: Bit Reload Timer Control Status Register (lower) Ch. N (tmcsrln)

16-bit reload timer reload register ch. n (TMRLRHn/TMRLRLn) is loaded to the 16-bit reload timer timer register ch. n (TMRHn/TMRLn), and the 16-bit reload timer continues counting. bit4 Details Writing "0" One-shot mode Writing "1" Reload mode FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 395

The read value is always "0". Writing "0" Has no effect on operation. The 16-bit reload timer starts counting from the next count clock input after the value set in Writing "1" TMRLRHn/TMRLRLn is reloaded to TMRHn/TMRLn. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 396: Bit Reload Timer Timer Register (upper/lower) Ch. N (tmrhn/tmrln)

• This register is read-only and located at the same address as the 16-bit reload timer reload register ch. n. Therefore, a write access to this register becomes a write access to the 16-bit reload timer reload register ch. n. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 397: Bit Reload Timer Reload Register (upper/lower) Ch. N (tmrlrhn/tmrlrln)

• This register is write-only and located at the same address as the 16-bit reload timer timer register ch. n. Therefore, a read access to this register becomes a read access to the 16-bit reload timer timer register ch. n. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 398: Notes On Using 16-bit Reload Timer

(UF) in the 16-bit reload timer control status register (lower) ch. n (TMCSRLn) is set to "1", the CPU cannot wake up from the interrupt service routine. Therefore, always clear the UF bit in the interrupt service routine. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 399: Chapter 21 Multi-pulse Generator

This chapter describes the specifications and operations of the multi-pulse generator. 21.1 Overview 21.2 Block Diagram 21.3 Pins 21.4 Interrupts 21.5 Operations 21.6 Registers 21.7 Notes on Using Multi-pulse Generator 21.8 Sample Program for Multi-pulse Generator MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 400

Triggered by the position detection input (SNI2 to SNI0). Triggered by the 16-bit reload timer underflow. The 16-bit reload timer is started by the position detection comparison circuit. Triggered either by the 16-bit reload timer underflow, or by the position detection input. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 401

PPG edge to synchronize with. Figure 21.1-1 PPG Rising Edge Synchronization Asynchronous State Change WTS[1:0] = 0b00 Glitch Synchronous State Change WTS[1:0] = 0b01 OP5’ OP4’ The sequencer changes its state (e.g. due to a reload timer underflow). MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 402

After above condition met, the writing timing signal will be generated for the data transfer between the OPDBRHx and OPDBRLx registers and the OPDUR and OPDLR registers. Furthermore, the edge detection for individual input (SNI2 to SNI0) can be disable/enable. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 403: Block Diagram

*2: See "■ Multi-pulse Generator Interrupt Sources" in "21.4 Interrupts". ● 16-bit PPG timer The 16-bit PPG timer is used to provide the PPG signal for the waveform sequencer. Details of the 16-bit PPG timer are described in "CHAPTER 19 16-BIT PPG TIMER". MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 404

WTS1 WTS0 CPIF CPIE CPD2 CPD1 CPD0 CMPE CPE1 CPE0 SNC2 SNC1 SNC0 SEE2 SEE1 SEE0 IPCLR Register Compare Match Interrupt Interrupt C* PDIRT NCCR Register *: See "■ Multi-pulse Generator Interrupt Sources" in "21.4 Interrupts". FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 405

The sync circuit is used to synchronize the OPT5 to OPT0 outputs with the PPG signal. ● 16-bit MPG noise cancellation control register (NCCR) The 16-bit MPG noise cancellation control register (NCCR) is used to select one of four sampling clock for the noise filter. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 406

● 16-bit MPG output data register (upper) (OPDUR) and 16-bit MPG output data register (lower) (OPDLR) The 16-bit MPG output data register (upper) (OPDUR) and the 16-bit MPG output data register (lower) (OPDLR) are used to store the output data to the OPT5 to OPT0 pins. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 407

The 16-bit MPG compare clear register (upper) (CPCUR) and the 16-bit MPG compare clear register (lower) (CPCLR) are used to store the 16-bit value which is used to compare the value of the 16-bit up counter. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 408

16-bit MPG output data buffer register 0 (upper/lower) (OPDBRH0/OPDBRL0) is written. ● Selector 0 The selector 0 is used to select from either WTIN1 of the position detect circuit or external pin (TI1) to enable the count of the 16-bit reload timer. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 409

OPS[2:0] bits: Table 21.2-1 TOUT Trigger Edge Selection for WTIN0 OPS2 OPS1 OPS0 TOUT Trigger Edge for WTIN0 Rise and Fall Fall Rise and Fall Rise and Fall Fall Initial value of the OPS[2:0] bits MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 410

The noise filter is used to filter out the noise of the input signal in which there are 4 kind of sampling clock for selection. ● Selector The selector is used to select from either edge detect circuit or comparison circuit to generate data write time output signal to the data write control unit. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 411

The TI1 pin functions as the input pin of the 16-bit reload timer for the multi-pulse generator. Set the corresponding bit in the port direction register (DDR) to "0" to use the TI1 pin as an input port. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 412

12 pairs of 16-bit MPG output data buffer register (upper/lower) (OPDBRHB and OPDBRLB - OPDBRH0 and OPDBRL0) to the 16-bit MPG output data register (upper/lower) (OPDUR/OPDLR). This write timing output can be FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 413

CPD[2:0] bits in the IPCUR register match with those of the RDA[2:0] bits in the OPDUR register. For the respective interrupt request numbers of interrupt sources, refer to "■ INTERRUPT SOURCE TABLE" in the device data sheet. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 414

■ Output Data Register Block Diagram Figure 21.5-1 Output Data Register Block Diagram 16-BIT RELOAD TIMER POSITION DETECT CIRCUIT 16-BIT PPG TIMER OUTPUT DATA REGISTER OP51/OP50 OPT5 OP41/OP40 OPT4 OP31/OP30 OPT3 OP21/OP20 OPT2 OP11/OP10 OPT1 OP01/OP00 OPT0 DTTI BNKF/RDA2 RDA1/RDA0 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 415

■ OPTx Output Waveform Timing Diagram (WTS[1:0] = 0b00) Figure 21.5-2 OPTx Output Waveform Timing Diagram (WTS[1:0] = 0b00) OPx1, OPx0 0b00 0b01 0b11 0b10 (OPDUR, OPDLR) OPTx PPG Output PPG Inverted Output "L" Output "H" Output MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 416: Operation Of Position Detection

■ Edge Detection Timing Diagram (CMPE = 0) Figure 21.5-3 Edge Detection Timing Diagram (CMPE = 0) CMPE CPE1, 0b01 0b11 0b10 CPE0 SNI2 SNI1 SNI0 WTIN1 RISING EDGE FALLING EDGE BOTH EDGES DETECTION DETECTION DETECTION FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 417

Detects SNIx rising edge and SNIx/RDAx comparison match. Detects SNIx falling edge and SNIx/RDAx comparison match. Detects SNIx both edges and SNIx/RDAx comparison match. Note: When CMPE = 1, SEEx should be set to "0", setting SEEx = 1 is not recommended. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 418: Operation Of Data Write Control Unit

The write timing output signal is generated from the data write control unit whenever a value is written to OPDBRH0 and OPDBRL0, and the data in OPDBRH0 and OPDBRL0 is transferred to OPDUR and OPDLR one cycle later. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 419

OUTPUT POSITION SNI2 to WTIN1 DETECTION SNI0 DATA WRITE CONTROL UNIT The 16-bit reload timer can be started by TIN input or a software trigger. The write signal is controlled by the 16-bit reload timer underflow. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 420

At this setting the16-bit reload timer is started by the compare match or effective edge input of the position detection circuit, write signal is then generated whenever the 16-bit reload timer is underflow. The compare match is triggered by any effective edge change in SNI2 to SNI0 pins. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 421

Figure 21.5-11 OPDUR and OPDLR Write Timing Diagram (OPS[2:0] = 0b001, 0b010, 0b011, 0b100, 0b101, 0b110, or 0b111) OPS[2:0] 0b001, 0b010, 0b011, 0b100, 0b101, 0b110, or 0b111 BNKF, 0b0001 0b0100 0b0111 RDA[2:0] (OPDUR) OPDBRL1[0] OPDBRL4[0] OPDBRL7[0] OP00 MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 422: Operation Of 16-bit Mpg Output Data Buffer Register (upper/lower Opdbrhx/opdbrlx)

Table 21.5-3 16-bit MPG output data buffer register (upper/lower) (OPDBRH, OPDBRL) BNKF RDA2 RDA1 RDA0 OP51 OP50 OP41 OP40 OP31 OP30 OP21 OP20 OP11 OP10 OP01 OP00 OPBDR No. Sequence OPT5 Output OPT4 Output OPT3 Output OPT2 Output OPT1 Output OPT0 Output FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 423

The data is transferred to the 16-bit MPG output data register (upper/lower) (OPDUR/OPDLR) sequentially. The 16-bit MPG output data buffer register (upper/lower) (OPDBRHx/ OPDBRLx) are not used if it is not set, e.g. No. 7 and No. 8 in Table 21.5-3. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 424: Operation Of Data Transfer Of 16-bit Mpg Output Data Register (upper/lower)

16-bit MPG output data register (upper). This does not apply to the OPDBRH0 and OPDBRL0 write method. In this write method, the BNKF bit and the RDA[2:0] bits are ignored. Always use the word access instruction to access OPDUR/OPDLR. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 425

Figure 21.5-12 Structure between OPDBRHx, OPDBRLx and OPDUR, OPDLR OPDBRH0, OPDBRL0 OPDBRH1, OPDBRL1 OPDBRH2, OPDBRL2 OPDBRH3, OPDBRL3 OPDBRH4, OPDBRL4 TO OUTPUT OPDBRH5, OPDBRL5 OPDUR, 12 TO 1 SELECTOR CONTROL OPDLR OPDBRH6, OPDBRL6 CIRCUIT OPDBRH7, OPDBRL7 OPDBRH8, OPDBRL8 OPDBRH9, OPDBRL9 OPDBRHA, OPDBRLA OPDBRHB, OPDBRLB MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 426: At Opdbrh0 And Opdbrl0 Write

Figure 21.5-13 Timing Generated by OPDBRH0 and OPDBRL0 Write (OPS[2:0] = 0b000) RDA[2:0] 0b000 0b110 0b001 (OPDUR) ODBR0W ODBR1W ODBR2W OP0[1:0] 0b00 0b01 0b11 (OPDLR) OPT0 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 427: At 16-bit Reload Timer Underflow

No. 3 No. 1 No. 6 No. 5 No. A No. 0 BNKF, RDA2, 0b0100 0b0110 0b0010 0b0011 0b0001 0b0101 0b1010 0b1011 RDA1, RDA0 OPT5 OPT4 OPT3 OPT2 OPT1 OPT0 Timer 16-bit reload timer underflow occurs starts MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 428

■ Timing Generated by Reload Timer Underflow (OPS[2:0] = 0b001) Figure 21.5-15 Timing Generated by Reload Timer Underflow (OPS[2:0] = 0b001) Reload timer counter action RDA[2:0] 0b100 0b110 0b101 0b011 0b001 (OPDUR) WTIN0 (TOUT) OP0[1:0] 0b00 0b01 0b11 0b00 0b10 (OPDLR) OPT0 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 429: At Position Detection

Write signal is generated when theres is a comparison match between RDA[2:0] and SNI2-SNI0 or any effective edge input at SNI2-SNI0. The comparison is triggered by the input edge position detection input terminal SNIx. SNI2 SNI1 SNI0 MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 430

■ Timing Generated by Position Detection (OPS[2:0] = 0b010) Figure 21.5-17 Timing Generated by Position Detection (OPS[2:0] = 0b010) SNI2 SNI1 SNI0 RDA[2:0] 0b100 0b110 0b101 0b011 0b001 (OPDUR) WTIN1 OP0[1:0] 0b00 0b01 0b11 0b00 0b10 0b11 (OPDLR) OPT0 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 431: At Position Detection And Timer Underflow

No. A BNKF, RDA2, 0b0100 0b0110 0b0010 0b0011 0b0001 0b0101 0b1010 0b1011 RDA1, RDA0 OPT5 OPT4 OPT3 OPT2 OPT1 OPT0 Write signal is generated by 16-bit reload timer underflow. 16-bit reload timer down-counting time SNI2 SNI1 SNI0 MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 432

16-bit reload timer. The operation of output data is renewed automatically. In order to use this method, use the 16-bit reload timer in one-shot mode. TIN0O must be longer than two machine cycles. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 433

Figure 21.5-19 Timing Generated by Position Detection and Timer Underflow (OPS[2:0] = 0b011) SNI2 SNI1 SNI0 TIN0O (TIN) Reload timer counter action RDA[2:0] 0b100 0b110 0b010 0b011 0b001 (OPDUR) WTIN0 (TOUT) OP0[1:0] 0b00 0b01 0b11 0b00 0b10 0b11 (OPDLR) OPT0 MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 434: At Position Detection Or Timer Underflow

SNI1 SNI0 Write signal is generated when theres is a comparison match between RDA[2:0] and SNI2-SNI0 or any effective edge input at SNI2-SNI0. The comparison is triggered by the input edge position detection input terminal SNIx. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 435

Figure 21.5-21 Timing Generated by Position Detection or Timer Underflow (OPS[2:0] = 0b100) SNI2 SNI1 SNI0 WTIN1 Reload Timer Counter Action RDA[2:0] 0b100 0b010 0b101 0b011 0b111 (OPDUR) WTIN0 (TOUT) OP0[1:0] 0b00 0b01 0b11 0b00 0b10 0b11 (OPDLR) OPT0 MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 436: At One-shot Position Detection

■ Timing Generated by One-shot Position Detection (OPS[2:0] = 0b110) Figure 21.5-22 Timing Generated by One-shot Position Detection (OPS[2:0] = 0b110) SNI2 SNI1 SNI0 RDA[2:0] 0b100 0b110 (OPDUR) WTIN1 OP0[1:0] 0b00 0b01 0b11 (OPDLR) OPT0 OPS[2:0] 0b110 0b010 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 437: When One-shot Position Detection And Reload Timer Underflow

Figure 21.5-23 Timing Generated by One-shot Position Detection and Reload Timer Underflow (OPS[2:0] = 0b111) SNI2 SNI0 TIN0O (TIN) Reload timer counter action RDA[2:0] 0b100 0b110 (OPDUR) WTIN0 (TOUT) OP0[1:0] 0b00 0b11 0b01 (OPDLR) OPT0 OPS[2:0] 0b111 0b011 MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 438: When One-shot Position Detection Or Reload Timer Underflow

Figure 21.5-24 Timing Generated by One-shot Position Detection or Reload Timer Underflow (OPS[2:0] = 0b101) SNI2 SNI1 SNI0 WTIN1 Reload timer counter action RDA[2:0] 0b101 0b010 (OPDUR) WTIN0 (TOUT) OP0[1:0] 0b00 0b01 0b11 (OPDLR) OPT0 OPS[2:0] 0b101 0b100 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 439: Operation Of Dtti Input Control

DTIE N can be 4, 8, 16, 32 depending on the N-CYCLE DELAY setting of D[1:0] bits CIRCUIT in the noise cancellation control register (NCCR). NOISE CANCELLATION SELECTOR NRSL DTIF DTTI INTERRURT AND CONTROL GENERATOR DTISP MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 440

* DTIF is cleared by writing “0” to it. Note: In the worst case the time from DTTI being recognized (after noise cancellation) to DTISP in effect takes 2 cycles, in best case it takes 1 cycle. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 441

DTTI has no effect on OPTx. DTTI takes effect. Noise filter is enabled. An "L" input at DTTI pin triggers the output of the inactive level set in PDRx. The DTTI interrupt is generated. DTTI has no effect on OPTx. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 442: Operation Of Noise Cancellation Function

16 MHz machine clock, the circuit can filter 0.25 µs to 2 µs width pulses. The control for the programming of the noise cancellation circuit of the SNIx and DTTI pins are separated. Section "21.6.9 16-bit MPG Noise Cancellation Control Register (NCCR)" shows the noise cancellation control register. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 443: Operation Of 16-bit Timer

An interrupt can be generated when the counter is cleared due to a match with the compare clear register. There is no interrupt when an overflow occurs. Note: To access the compare clear register and the timer buffer register, the word access instruction must be used. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 444

0xBFFF 0x7FFF 0x3FFF 0x0000 Time Reset Interrupt Figure 21.5-28 Clearing the Counter upon a Match with Compare Clear Register Counter value 0xFFFF Match Match 0xBFFF 0x7FFF 0x3FFF Time 0x0000 Reset Compare clear 0xBFFF register value Interrupt FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 445

Write Timing signal or the Position Detection signal, the counter is cleared in synchronization with the count timing. Figure 21.5-30 16-bit Timer Clear Timing MCLK Compare register value Prescaler clock Compare match 0x0000 0x0001 N - 1 0x0002 Counter value MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 446

■ 16-bit Timer Buffer Operation Timing Diagram Figure 21.5-31 16-bit Timer Buffer Operation Timing Diagram CPU clock Counter value 0x0000 0x0001 0x0002 0x0000 0x0001 0x0002 Timer buffer 0xXXXX 0x0002 MODE 0 or 1 (TCSR) Buffer load signal TMEN WTIN1 Timer reset FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 447

Counter value Current counter value is latched into buffer. Timer is reset, which is triggered Timer is reset, which is triggered by write timing or position detection. by write timing or position detection. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 448

16-bit MPG compare clear register (lower) 21.6.6 TMBUR 16-bit MPG timer buffer register (upper) 21.6.7 TMBLR 16-bit MPG timer buffer register (lower) 21.6.7 TCSR 16-bit MPG timer control status register 21.6.8 NCCR 16-bit MPG noise cancellation control register 21.6.9 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 449: Bit Mpg Output Control Register (upper) (opcur), Bit Mpg Output Control Register (upper)

The DTTI pin input will pass through the noise filter. Note: When the noise cancellation circuit is enabled, the DTTI pin input becomes invalid in a mode such as stop mode in which the internal clock is stopped. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 450

When this bit is set to "1", and the write timing interrupt request flag bit (WTIF) is also set to "1", a write timing interrupt is generated. bit0 Details Writing "0" Disables the write timing interrupt. Writing "1" Enables the write timing interrupt. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 451: Bit Mpg Output Control Register (lower) (opclr), Bit Mpg Output Control Register (lower)

Disables the position detection interrupt. Writing "1" Enables the position detection interrupt. [bit5] OPE5: OPT5 output enable bit This bit enables or disables OPT5 pin output. bit5 Details Writing "0" Disables OPT5 pin output. Writing "1" Enables OPT5 pin output. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 452

Disables OPT1 pin output. Writing "1" Enables OPT1 pin output. [bit0] OPE0: OPT0 output enable bit This bit enables or disables OPT0 pin output. bit0 Details Writing "0" Disables OPT0 pin output. Writing "1" Enables OPT0 pin output. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 453: Bit Mpg Output Data Register (upper/lower) (opdur/opdlr)

For details of the 16-bit MPG output data register (upper) (OPDUR), see "21.6.3.1 16-bit MPG Output Data Register (Upper) (OPDUR)". for details of the 16-bit MPG output data register (lower) (OPDLR), see "21.6.3.2 16-bit MPG Output Data Register (Lower) (OPDLR)". MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 454: Bit Mpg Output Data Register (upper) (opdur), Bit Mpg Output Data Register (upper)

Indicates that the output of the PPG timer is output to the OPT5 pin. Reading "10" Indicates that the inverted output is output to the OPT5 pin. Reading "11" Indicates that "H" level is output to the OPT5 pin. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 455

Indicates that the output of the PPG timer is output to the OPT4 pin. Reading "10" Indicates that the inverted output is output to the OPT4 pin. Reading "11" Indicates that "H" level is output to the OPT4 pin. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 456: Bit Mpg Output Data Register (lower) (opdlr), Bit Mpg Output Data Register (lower)

Indicates that the output of the PPG timer is output to the OPT0 pin. Reading "10" Indicates that the inverted output is output to the OPT0 pin. Reading "11" Indicates that "H" level is output to the OPT0 pin. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 457: Bit Mpg Output Data Buffer Register (upper/lower) (opdbrhx/opdbrlx)

For details of the 16-bit MPG output data buffer register (upper) (OPDBRHx), see "21.6.4.1 16-bit MPG Output Data Buffer Register (Upper) (OPDBRHx)". For details of the 16-bit MPG output data buffer register (lower) (OPDBRLx), see "21.6.4.2 16-bit MPG Output Data Buffer Register (Lower) (OPDBRLx)". MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 458: Bit Mpg Output Data Buffer Register (upper) (opdbrhx), Bit Mpg Output Data Buffer Register (upper)

Selects the output of the PPG timer as the waveform to be output to the OPT5 pin. Writing "10" Selects the inverted output as the waveform to be output to the OPT5 pin. Writing "11" Selects "H" level as the waveform to be output to the OPT5 pin. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 459

Selects the output of the PPG timer as the waveform to be output to the OPT4 pin. Writing "10" Selects the inverted output as the waveform to be output to the OPT4 pin. Writing "11" Selects "H" level as the waveform to be output to the OPT4 pin. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 460: Bit Mpg Output Data Buffer Register (lower) (opdbrlx), Bit Mpg Output Data Buffer Register (lower)

Selects the output of the PPG timer as the waveform to be output to the OPT1 pin. Writing "10" Selects the inverted output as the waveform to be output to the OPT1 pin. Writing "11" Selects "H" level as the waveform to be output to the OPT1 pin. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 461

Selects the output of the PPG timer as the waveform to be output to the OPT0 pin. Writing "10" Selects the inverted output as the waveform to be output to the OPT0 pin. Writing "11" Selects "H" level as the waveform to be output to the OPT0 pin. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 462: Bit Mpg Input Control Register (upper/lower) (ipcur/ipclr)

For details of the 16-bit MPG input control register (upper) (IPCUR), see "21.6.5.1 16-bit MPG Input Control Register (Upper) (IPCUR)". For details of the 16-bit MPG input control register (lower) (IPCLR), see "21.6.5.2 16-bit MPG Input Control Register (Lower) (IPCLR)". FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 463: Bit Mpg Input Control Register (upper) (ipcur), Bit Mpg Input Control Register (upper)

When this bit is set to "1", and the compare interrupt request flag bit (CPIF) is also set to "1", a compare interrupt is generated. bit4 Details Writing "0" Disables the compare interrupt. Writing "1" Enables the compare interrupt. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 464

If the RDA[2:0] bits are "111", a compare match occurs. [bit0] CMPE: Position detection compare enable bit This bit enables or disables the compare operation in position detection. bit0 Details Writing "0" Disables the compare operation. Writing "1" Enables the compare operation. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 465: Bit Mpg Input Control Register (lower) (ipclr), Bit Mpg Input Control Register (lower)

SNI1 input does not pass through the noise cancellation circuit. Writing "1" SNI1 input passes through the noise cancellation circuit. bit3 Details Writing "0" SNI0 input does not pass through the noise cancellation circuit. Writing "1" SNI0 input passes through the noise cancellation circuit. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 466

Set this bit before setting the CMPE bit in the input control register (upper) (IPCUR) to "0". bit0 Details Writing "0" Disables the edge detection on the SNI0 pin. Writing "1" Enables the edge detection on the SNI0 pin. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 467: Bit Mpg Compare Clear Register (upper/lower) (cpcur/cpclr)

16-bit MPG compare clear register (lower) (CPCLR) are the same as the 16-bit timer counter value, the compare operation will not be performed until the next occasion in which the values of CPCUR and CPCLR are the same as the 16-bit timer counter value. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 468: Bit Mpg Timer Buffer Register (upper/lower) (tmbur/tmblr)

Use the "MOVW" instruction (use a 16-bit access instruction to read the TMBUR register address). • Use the "MOV" instruction to read or write TMBUR first and then TMBLR. ■ Register Configuration TMBUR Field Attribute Initial value TMBLR Field Attribute Initial value FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 469: Bit Mpg Timer Control Status Register (tcsr)

Reading "0" Indicates that no compare clear interrupt request has been generated. Reading "0" Indicates that a compare clear interrupt request has been generated. Writing "0" Clears this bit. Writing "1" Has no effect on operation. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 470

8 µs 16 µs 32 µs 128 µs Note: Since the count clock is changed immediately after these bits are updated, it is recommend to modify these bits while the 16-bit timer is in stop state. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 471: Bit Mpg Noise Cancellation Control Register (nccr), Bit Mpg Noise Cancellation Control Register

[bit1:0] D[1:0]: DTTI noise width select bits These bits select the noise width to be cancelled on the DTTI pin. bit1:0 Details Writing "00" 4-machine cycle noise Writing "01" 8-machine cycle noise Writing "10" 16-machine cycle noise Writing "11" 32-machine cycle noise MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 472: Notes On Using Multi-pulse Generator

(NCCR), ensure that the noise cancellation function has been disabled (OPCUR:NRSL = 0). • Before modifying the S2[1:0], S1[1:0] and S0[1:0] bits in the NCCR register, ensure that the noise cancellation function has been disabled (IPCLR:SNC[2:0] = 0b000). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 473

MPG and cannot work independently of the MPG. When the 16-bit PPG timer or the 16-bit reload timer is needed for other applications, disable the MPG first before using them for other applications. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 474: Sample Program For Multi-pulse Generator

;Assumes that stack pointer (SP) has already been CLRI ;Interrupt disable ILR4,#00H ;Interrupt level 0 (top priority) MOVW A,#0064H MOVW PCSR1,A ;Sets the period of the PPG output MOVW A,#003CH MOVW PDUT1,A ;Sets the duty ratio of the PPG output MOVW A,#01100000000000110B FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 475

; User processing RETI ;Returns from interrupt CODE ENDS ;-------Vector setting------------------------------------------------------------------------------------------ VECT CSEG 0FFDAH ;Sets vector for interrupt #16 (0x10) DW WARI 0FFFCH ;Sets reset vector DW 0000H ;Sets single-chip mode DW START VECT ENDS START MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 476

CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.8 Sample Program for Multi-pulse Generator FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 477: Chapter 22 Uart/sio

CHAPTER 22 UART/SIO This chapter describes the functions and operations of UART/SIO. 22.1 Overview 22.2 Configuration 22.3 Channel 22.4 Pins 22.5 Interrupts 22.6 Operations and Setting Procedure Example 22.7 Registers MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 478

Operation mode 0 operates as clock asynchronous mode (UART). Operation mode 1 operates as clock synchronous mode (SIO). Table 22.1-1 UART/SIO Operation Modes Data length Synchronization Operation mode Length of stop bit mode No parity With parity Asynchronous 1 bit or 2 bits Synchronous FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 479

Shift UART/SIO register serial output Serial data output data register for trans- Transmis- Parity ch. n mission sion bit operation count UART/SIO Port control serial mode control Set to registers 1, 2 each block ch. n MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 480

This register sets the transmit data. Data written to this register is serial-converted and then output. ■ Input Clock The UART/SIO uses the output clock (internal clock) from the dedicated baud rate generator or the input signal (external clock) from the UCKn pin as its input clock (serial clock). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 481

UART/SIO serial mode control register 1 ch. n SMC2n UART/SIO serial mode control register 2 ch. n SSRn UART/SIO serial status and data register ch. n TDRn UART/SIO serial output data register ch. n RDRn UART/SIO serial input data register ch. n MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 482

● UIn Serial data input pin for UART/SIO. When it is to be used as a UART/SIO serial data input pin, make sure that it is set as input port by the corresponding port direction register. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 483

FER) is set to "1". These bits are set when a stop bit is detected. If receive interrupt enable bit has been enabled (SMC2n:RIE = 1), an interrupt request to the interrupt controller will be generated. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 484

*: For details of the interrupt level setting register (ILR), refer to "CHAPTER 5 INTERRUPTS" in this hardware manual and "■ INTERRUPT SOURCE TABLE" in the device data sheet. ● Interrupt processing Read receive data. (RDRn) FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 485: Operations In Operation Mode 0

1 (Setting value: 0,0) 28736 45977 46695 1 (Setting value: 0,0) 19231 30769 31250 2 (Setting value: 0,1) 1040 9615 15385 15625 4 (Setting value: 1,0) 2080 4808 7692 7813 8 (Setting value: 1,1) 4160 2404 3846 3906 MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 486

Without P 8-bit data With P : Start bit : Stop bit : Parity bit D0 to D7: Data. The sequence can be selected from "LSB first" or "MSB first" by the direction control register (BDS bit) FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 487

The data received up to that point will not be transferred to the serial input data register. Figure 22.6-3 Receive Operation in Clock Asynchronous Mode (UART) D0 D1 D2 D3 D4 D5 D6 Sp Sp D0 D1 D2 RDRn read RDRF MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 488

Upon completion of reception of serial data, the overrun error bit (OVE) is set to "1" if the reception of the next data is performed before the previous receive data is read. Each flag is set at the position of the first stop bit. Figure 22.6-4 Setting Timing for Receive Errors Receive interrupt FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 489

"L" "L" Start bit detection Counter divided by 4 Data sampling clock (DSCLK) Sampling at three points to determine "0" or "1" on a majority basis when two bits out of three match Reception shift register MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 490

Figure 22.6-6 Transmission in Clock Asynchronous Mode (UART) TCPL TDRE Transmit interrupt When the STOP bit length is set to 1 bit When the STOP bit length is set to 2 bits FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 491

In clock asynchronous mode (UART), transmission and reception can be performed independently. Therefore, transmission and reception can be performed at the same time or even with transmitting and receiving frames overlapping each other in shifted phases. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 492: Operations In Operation Mode 1

Figure 22.6-9 Calculating Baud Rate Based on External Clock Baud rate value = [bps] External clock* More than 4 machine clock *: External clock More than 4 machine clock FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 493

The serial clock signal is output under control of the output for transmit data. When only reception is performed, therefore, set transmission control (SMC2n:TXE = 1) to write dummy transmit data to the UART/SIO serial output register. Refer to the device data sheet for the UCKn clock value. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 494

UART/SIO serial output data register to generate the serial clock signal and start reception. • Write transmit data to the TDRn register, then set the TXE bit to "1" to generate the serial clock signal and start reception. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 495

"1" by the reception for the preceding piece of data. Figure 22.6-13 Overrun Error UCKn D0 D1 ... D6 D7 D0 D1 ... D6 D7 D0 D1 ... D6 D7 Read to RDRn RDRF MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 496

When the transmit data is written to the TDRn register, the TDRE bit is cleared to "0". When serial transmission is started after transmit data is transferred from the TDRn register to the transmission shift register, the TDRE bit is set to "1". FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 497

As the transmitting side generates a serial clock, reception is influenced. If transmission stops during reception, the receiving side is suspended. It resumes reception when the transmitting side is restarted. See "22.4 Pins" for operation with serial clock output and operation with serial clock input. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 498

UART/SIO serial mode control register 2 ch. n 22.7.2 SSRn UART/SIO serial status and data register ch. n 22.7.3 RDRn UART/SIO serial input data register ch. n 22.7.4 TDRn UART/SIO serial output data register ch. n 22.7.5 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 499: Uart/sio Serial Mode Control Register 1 Ch. N (smc1n)

Note: The setting of this bit is only valid for transmission operation in clock asynchronous mode (UART). In a receive operation, regardless of the setting of this bit, the UART/SIO completes the receive operation when detecting a stop bit (one bit), and sets the receive data register full flag bit (SSRn:RDRF) to "1". MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 500

Details Writing "0" Clock asynchronous mode (UART) Writing "1" Clock synchronous mode (SIO) Note: During data transmission or reception, do not modify the settings of the UART/SIO serial mode control register 1 ch. n (SMC1n). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 501: Uart/sio Serial Mode Control Register 2 Ch. N (smc2n)

This bit clears the receive error flags. The read value of this bit is always "1". bit5 Details Writing "0" Clears the receive error flags (PER, OVE and FER) in the SSRn register. Writing "1" Has no effect on operation. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 502

(SSRn:TDRE) is set to "1". bit0 Details Writing "0" Disables the transmit data register empty interrupt. Writing "1" Enables the transmit data register empty interrupt. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 503: Uart/sio Serial Status And Data Register Ch. N (ssrn)

When a framing error is detected at the same time as clearing this bit by writing "0" to the RERC bit, setting this bit to "1" is given priority. bit3 Details Reading "0" Indicates that no framing error has occurred. Reading "1" Indicates that a framing error has occurred. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 504

When transmit data is loaded to the shift register for the transmission and data transmission starts, this bit is set to "1". bit0 Details Reading "0" Indicates that there is transmit data in the TDRn register. Reading "1" Indicates that there is no transmit data in the TDRn register. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 505: Uart/sio Serial Input Data Register Ch. N (rdrn)

RDRF bit to "0". When the character bit length (SMC1n:CBL[1:0]) is set to shorter than eight bits, the excess upper bits (beyond the set bit length) are set to "0". MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 506: Uart/sio Serial Output Data Register Ch. N (tdrn)

TCPL bit is not set to "1". In the case of modifying the transmit data, make the TDRE bit become "1" once by writing "0" to the TXE bit before modifying the transmit data. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 507: Chapter 23 Uart/sio Dedicated Baud Rate Generator

CHAPTER 23 UART/SIO DEDICATED BAUD RATE GENERATOR This chapter describes the functions and operations of the dedicated baud rate generator for the UART/SIO. 23.1 Overview 23.2 Channel 23.3 Operations 23.4 Registers MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 508

The UART/SIO dedicated baud rate generator uses the output clock from the prescaler or the machine clock as its input clock. ■ Output Clock The UART/SIO dedicated baud rate generator supplies its clock to the UART/SIO. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 509

Table 23.2-1 Registers of Dedicated Baud Rate Generator Register Corresponding register (Name in this manual) abbreviation PSSRn UART/SIO dedicated baud rate generator prescaler select register ch. n BRSRn UART/SIO dedicated baud rate generator baud rate setting register ch. n MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 510

3846 3906 The baud rate can be set in UART mode within the following range. Table 23.3-2 Baud Rate Setting Range in Clock Asynchronous Mode (UART) PSS[1:0] BRS[7:0] 0b00 to 0b11 0x02 (2) to 0xFF (255) FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 511

Table 23.4-1 List of UART/SIO Baud Rate Generator Registers Register Register name Reference abbreviation PSSRn UART/SIO dedicated baud rate generator prescaler select register ch. n 23.4.1 BRSRn UART/SIO dedicated baud rate generator baud rate setting register ch. n 23.4.2 MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 512

Writing "0" Disables outputting the baud rate clock. Writing "1" Enables outputting the baud rate clock. [bit1:0] PSS[1:0]: Prescaler select bits These bits select a prescaler. bit1:0 Details Writing "00" Writing "01" Writing "10" Writing "11" FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 513

This register sets the cycle of the 8-bit downcounter and can be used to set any baud rate clock (BRCLK). Stop the UART/SIO operation before writing a value to this register. In clock asynchronous mode (UART), do not set BRS[7:0] to "0x00" or "0x01". MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 514

CHAPTER 23 UART/SIO DEDICATED BAUD RATE GENERATOR MB95630H Series 23.4 Registers FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 515

This chapter describes functions and operations of the I C bus interface. 24.1 Overview 24.2 Configuration 24.3 Channel 24.4 Pins 24.5 Interrupts 24.6 Operations and Setting Procedure Example 24.7 Registers 24.8 Notes on Using I C Bus Interface MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 516

C bus interface includes a function to wake up the MCU from standby mode. Figure 24.1-1 Example of I C Bus Interface Configuration Static RAM/ Microcontroller A LCD driver EEPROM SDAn SCLn Gate array A/D converter Microcontroller B FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 517

In this chapter, "n" in a pin name and a register abbreviation represents the channel number. For details of pin names, register names and register abbreviations of a product, refer to the device data sheet. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 518

Start/stop condition ACK enable generation circuit GC-ACK enable DACKE Address ACK enable GACKE INT timing select IDDRn register IBSRn Slave Slave address comparison circuit General call IAARn register IBCR0n AACKX INTS SCLn line SDAn line Stop interrupt FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 519: Chapter 24 I 2 C Bus Interface

The IDDRn register holds the transmit or receive shift data or address. When transmitted, the data or address written to this register is transferred from the MSB first to the bus. ■ Input Clock The I C bus interface uses the machine clock as the input clock (shift clock). MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 520

C bus control register 0 ch. n IBCR1n C bus control register 1 ch. n IBSRn C bus status register ch. n IDDRn C data register ch. n IAARn C address register ch. n ICCRn C clock control register ch. n FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 521

The SCLn pin is the serial clock I/O pin of the I C bus interface. When the I C bus interface is enabled (ICCRn:EN = 1), the SCLn pin is automatically set as a shift clock I/O pin to function as the SCLn pin. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 522

(IBCR1n:BEIE = 1). In the interrupt service routine, write "0" to the bus error interrupt request flag bit (IBCR1n:BER) to clear the interrupt request. When a bus error occurs, the IBCR1n:BER bit is set to "1" regardless of the value of the IBCR1n:BEIE bit. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 523

MCU from stop or watch mode has been enabled (IBCR0n:WUE = 1). In the interrupt service routine, write "0" to the MCU standby mode wakeup interrupt request flag bit (IBCR0n:WUF) to clear the interrupt request. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 524

*: For details of the interrupt level setting register (ILR), refer to "CHAPTER 5 INTERRUPTS" in this hardware manual and "■ INTERRUPT SOURCE TABLE" in the device data sheet. ● Interrupt processing 1. Execute any process. 2. Clear the bus error interrupt request flag. (IBCR1n:BER = 0) FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 525

Data transfer is always ended in the master stop condition (P). However, the repeated start condition (S) can be used to transmit the address which indicates a different slave without generating a stop condition. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 526

"H". Data is transferred at one clock pulse per bit with MSB at the head. Sending and receiving an acknowledgment is required after each byte is transferred. Accordingly, nine clock pulses are required to transfer one complete data byte. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 527

SCLn cycle). Accordingly, if ACK is read when the IBCR0n:INTS bit is "1", you must write "0" to this bit in the transfer completion interrupt triggered by the eighth SCLn cycle so that another transfer completion interrupt will be triggered by the ninth SCLn cycle. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 528

If arbitration lost was detected, the module goes to slave mode and continues to receive data from the master. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 529

If the program triggers a start condition (by setting the IBCR1n:MSS bit to "1") when no start condition has been detected (IBSRn:BB = 0) and the SDAn and SCLn line pins are at the "L" level. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 530

SCLn pin or SDAn pin at "L" level "L" SCLn pin "L" SDAn pin C operation enabled (ICCRn:EN = 1) Master mode set (IBCR1n:MSS = 1) Arbitration lost detection bit (IBCR0n:ALF = 1) Bus busy (IBSRn:BB) Interrupt (IBCR1n:INT) FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 531

(Normal control means writing "0" to the IBCR1n:INT bit in the INT interrupt to clear IBCR0n:ALF to "0".) In other cases, perform control as normal (Normal control means writing "0" to the IBCR1n:INT bit in the INT interrupt to clear IBCR0n:ALF.) MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 532

Figure 24.6-6 Timing Diagram with Interrupt Generated with "IBCR0n:ALF = 1" Detected Interrupt in 9th clock cycle START condition SCLn pin Slave address Data SDAn pin ICCRn:EN IBCR1n:MSS Clear IBCR0n:ALF by software. IBCR0n:ALF IBSRn:BB Clear IBCR1n:INT by software IBCR1n:INT and release SCLn line. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 533: Function To Wake Up The Mcu From Standby Mode

To receive the data byte correctly, the SCLn must be released in the first cycle after 100 s (assuming a minimum oscillation stabilization wait time of 100 s) from the start of I C transmission (falling edge detection of SDAn). MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 534

Figure 24.6-8 Sample Flow Chart 2 Procedure for transition to stop/watch mode IBSRn:BB = 0 Enable wakeup function by setting IBCR0n:WUE =1. IBSRn:BB = 0 IBCR0n:WUE = 0 Write "0" to IBCR0n:ALE Go to stop/watch mode. and clear AL interrupt FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 535

C bus control register 1 ch. n IBSRn 24.7.3 C bus status register ch. n IDDRn 24.7.4 C data register ch. n IAARn 24.7.5 C address register ch. n ICCRn 24.7.6 C clock control register ch. n MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 536

• If the data acknowledge depends on the content of the received data (such as packet error checking used by the SM bus), control the data acknowledge by setting the data acknowledge enable bit (IBCR1n:DACKE) after writing "1" to this bit (for example, using a previous transfer completion interrupt) to read latest received data. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 537

When read by the read-modify-write (RMW) type of instruction, this bit always returns "1". bit3 Details Reading "0" Indicates that no STOP condition has been detected. Reading "1" Indicates that a STOP condition has been detected. Writing "0" Clears this bit. Writing "1" Has no effect on operation. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 538

The values of the AACKX, INTS, and WUE bits in the IBCR0n register become "0" and non-writable either when the I C operation is disabled (ICCRn:EN = 0) or when a bus error occurs (IBCR1n:BER = 1). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 539

This bit enables or disables the bus error interrupt. When this bit and the BER bit are both set to "1", a bus error interrupt request is generated. bit6 Details Writing "0" Disables the bus error interrupt. Writing "1" Enables the bus error interrupt. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 540

SCLn cycle during data reception. In slave mode, a data acknowledge is output in the ninth SCLn cycle only when an address acknowledgment has already been output. bit3 Details Writing "0" Disables data acknowledge output. Writing "1" Enables data acknowledge output. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 541

• During data reception, with the IBCR0n:INTS bit already set to "1", this bit becomes "1" after 1-byte data (not including an acknowledge) transfer is completed. If the INTS bit is set to "0", this bit becomes "1" after the transmission/reception of 1-byte data/address (including an acknowledge) is completed. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 542

• All bits in the IBCR1n register except the BER and BEIE bits are cleared to "0" either when the I C bus interface operation is disabled (ICCRn:EN = 0) or when a bus error occurs (IBCR1n:BER = 1). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 543

Indicates that the bus is in use and a repeated START condition has been detected. [bit5] Undefined bit The read value of this bit is always "0". Writing a value to this bit has no effect on operation. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 544

This bit is set to "0" when a START condition or a STOP condition has been detected. bit2 Details Reading "0" Indicates that the MCU has not undergone addressing in slave mode. Reading "1" Indicates that the MCU has undergone addressing in slave mode. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 545

• In slave mode, the device receives a general call address, but the IBCR1n:GACKE bit is "0". bit0 Details Reading "0" Indicates that the receive data is not the first byte in data reception. Reading "1" Indicates that the receive data is the first byte (address) in data reception. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 546

The received data or address can be read from this register at the transfer completion interrupt (IBCR1n:INT = 1). However, since the serial transfer register is directly read from when the received data or address is read, the receive data is valid only when the INT bit is "1". FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 547

■ Register Functions [bit7] Undefined bit The read value of this bit is always "0". Writing a value to this bit has no effect on operation. [bit6:0] A[6:0]: Address bits These bits set the slave address. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 548

• "0" is written to this bit. • The BER bit in the IBCR1n register is set to "1". bit5 Details Writing "0" Disables the I C bus interface operation. Writing "1" Enables the I C bus interface operation. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 549

Writing "100" Writing "101" Writing "110" Writing "111" Note: If the standby mode wakeup function is not used, disable the I C bus interface operation before making the MCU transit to stop mode or watch mode. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 550

In slave mode, a data acknowledge is generated if one of the following conditions is satisfied. - The received address matches the value in the address register (IAARn) and IBCR0n:AACKX is "0". - A general call address (0x00) is received and IBCR1n:GACKE is "1". FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 551

IBCR0n:WUE to "0" after the MCU wakes up from stop mode or watch mode, regardless of whether the MCU has been woken up by to the I C wakeup function or the wakeup function of another resource (such as an external interrupt). MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 552

CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.8 Notes on Using I C Bus Interface FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 553: Chapter 25 Example Of Serial Programming Connection

CHAPTER 25 EXAMPLE OF SERIAL PROGRAMMING CONNECTION This chapter describes the example of serial programming connection. 25.1 Basic Configuration of Serial Programming Connection 25.2 Example of Serial Programming Connection MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 554: Basic Configuration Of Serial Programming Connection

1-line UART Flash memory (MB2146-07-E/ product user system MB2146-08-E) Table 25.1-1 Pins Used for Fujitsu Semiconductor Standard Serial Onboard Programming Function Details Power supply voltage The programming voltage (2.4 V to 5.5 V) is supplied from the user system. supply pin GND pin It is shared with the GND of the Flash microcontroller programmer.
Page 555: Example Of Serial Programming Connection

The MCU enters the PGM mode at the following timing. ■ MCU Transiting to PGM Mode The MCU enters the PGM mode at the following timing. The serial programmer controls the DBG pin according to V input. Figure 25.2-1 Timing Diagram Transition to PGM Mode MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 556

In the case of using the BGM adaptor MB2146-07-E of Fujitsu Semiconductor Limited, it is recommended to use a pull-up resistor of approximately 2 k to 10 k .
Page 557: Chapter 26 Dual Operation Flash Memory

26.1 Overview 26.2 Sector/Bank Configuration 26.3 Invoking Flash Memory Automatic Algorithm 26.4 Checking Automatic Algorithm Execution Status 26.5 Programming/Erasing Flash Memory 26.6 Operations 26.7 Flash Security 26.8 Registers 26.9 Notes on Using Dual Operation Flash Memory MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 558

(upper bank/lower bank) simultaneously. The dual operation Flash can use the following combinations: Upper bank Lower bank Read Read Program/sector erase Program/sector erase Read Chip erase Sector erase (erase suspend) Program Program Sector erase (erase suspend) FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 559

In addition, it is not necessary to download a program to RAM in order to program data to a bank, thereby reducing the time of program download and eliminating the need to protecting RAM data against power interruption. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 560: Sector/bank Configuration

SA1: 2 Kbyte SA1: 2 Kbyte 0x1FFF 0x2000 0x7FFF 0x8000 0xBFFF Upper SA2: 32 Kbyte bank 0xC000 0xDFFF Upper SA2: 16 Kbyte bank 0xE000 0xEFFF Upper SA2: 8 Kbyte bank 0xF000 Upper SA2: 4 Kbyte bank 0xFFFF FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 561: Invoking Flash Memory Automatic Algorithm

SA : Sector address (Specify any address in a sector.) PD : Program data : The upper four bits represent an address in a sector to which data can be programmed. : Any address value any : Any program data MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 562

0 (SWRE0) has been set to "0" (to disable programming data to that sector). ■ Note on Issuing Commands Enable programming data into a required sector before issuing the first command in the command sequence table. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 563: Checking Automatic Algorithm Execution Status

DQ2, DQ3, DQ5, DQ6 and DQ7 flags. • The hardware sequence flags can also be used to check whether the second sector erase code write and those to be executed afterward are valid or not. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 564

Sector erase suspended Erasing Toggle Toggle resumed (Sector being erased) Sector erase being suspended DATA: 7 DATA: 6 DATA: 5 DATA: 3 DATA: 2 (Sector not being erased) Programming Toggle Abnormal operation Chip/sector erase Toggle Toggle FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 565: Data Polling Flag (dq7)

(DATA:7) of the value read from the read address to DQ7. • Referring the data polling flag (DQ7) together with the toggle bit flag (DQ6) permits a decision on whether Flash memory is in the sector erase suspended state or which sector is being erased. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 566

Data reading is allowed after the data polling flag (DQ7) is set to "1". Data reading after the end of the automatic algorithm should be performed following read access made to confirm the completion of data polling. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 567: Toggle Bit Flag (dq6)

See the notes in "26.9 Notes on Using Dual Operation Flash Memory" when writing a program. The note above does not apply if the Flash memory write control program is executed on the RAM. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 568: Execution Timeout Flag (dq5)

"1". The state in which the execution time-out flag (DQ5) outputs "1" means that the Flash memory has not been used correctly; it does not mean that the Flash memory is defective. When this state occurs, execute the reset command. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 569: Sector Erase Timer Flag (dq3)

"1" if the read address of that read access is the address of a sector being erased. If the read address is not the address of a sector being erased, the Flash memory outputs bit3 (DATA: 3) of the value read from the read address. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 570: Toggle Bit2 Flag (dq2)

With a sector erase operation suspended, when read accesses are continuously made to a sector not to be erased, the Flash memory outputs bit2 (DATA: 2) of the read value of a read address whenever a read access is made. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 571: Programming/erasing Flash Memory

The operations are explained in the following order: • Enter the read/reset state • Program data • Erase all data (chip erase) • Erase arbitrary data (sector erase) • Suspend sector erase • Resume sector erase • Unlock bypass program MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 572: Placing Flash Memory In Read/reset State

In the read/reset state, data in the Flash memory can be read by a read access to the Flash memory. • In the case of a read access to the Flash memory, no read/reset commands are required. If a command does not terminate normally, use a read/reset command to initialize the automatic algorithm. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 573: Programming Data To Flash Memory

(DQ7) even when the execution timeout flag (DQ5) is "1". • Similarly, since the toggle bit flag (DQ6) stops toggling at the same time as the execution timeout flag (DQ5) changes to "1", check DQ6 after DQ5 changes to "1". MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 574

(4) Program address Program data Read internal address. Next address Data Data polling (DQ7) Data Execution timeout (DQ5) Read internal address. Data Data polling (DQ7) Data Last address? Program error FSR:WRE Disable Flash memory programming. End of programming FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 575: Erasing All Data From Flash Memory (chip Erase)

0 (SWRE0) has been set to "0" (to disable programming data to that sector). • During chip erase, if a hardware reset occurs, the integrity of data in the Flash memory is not guaranteed. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 576: Erasing Specific Data From Flash Memory (sector Erase)

■ Note on Erasing Data from Sectors If a hardware reset occurs while data is being erased, the integrity of data in the Flash memory is not guaranteed. Therefore, run the sector erase procedure again after a hardware reset occurs. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 577

Set remainder re-execution flag, and terminate erase once Execution timeout (DQ5) Read internal address. Read internal address. Toggle bit (DQ6) Data 1 = Data 2 Remainder Erase error re-execution flag? FSR:WRE Disable Flash memory erasing. End of erasing MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 578: Suspending Sector Erase From Flash Memory

To suspend sector erase command again after resuming sector erase by issuing a sector erase resume command, issue the command after 2 ms or longer has elapsed since the issue of the sector erase resume command. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 579: Resuming Sector Erase Of Flash Memory

The sector erase resume command is executed by writing erase resume code (0x30). Specify an address in the sector selected to be erased. • A sector erase resume command input during sector erase is ignored. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 580: Unlock Bypass Program

If an unlock bypass reset command is input in the unlock bypass state, the Flash memory will return to the normal command state from the unlock bypass state. In addition, executing a hardware reset in the unlock bypass state will also make Flash memory return to the normal command state. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 581

Update data in lower bank Update data in upper bank Copy data Start program operation from SA2 to SA1 Set FSR:SSEN to "1" Start program operation Complete Complete Flash data update Flash data update Set FSR:SSEN to "0" MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 582

While data is being written to or erased from the Flash memory, state transition in the current mode (clock mode or standby mode) is prohibited. Ensure that programming data to or erasing data from the Flash memory ends before state transition occurs. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 583: Flash Security

It is advisable to write the protection code at the end of Flash programming to avoid enabling unnecessary protection during writing. Once Flash security is enabled, a chip erase operation must be executed before data can be written to the Flash memory again. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 584

FSR2 Flash memory status register 2 26.8.1 Flash memory status register 26.8.2 SWRE0 Flash memory sector write control register 0 26.8.3 FSR3 Flash memory status register 3 26.8.4 FSR4 Flash memory status register 4 26.8.5 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 585: Flash Memory Status Register 2 (fsr2)

Indicates that the device is in the command input wait state or Flash memory programming is in Reading "0" progress. Reading "1" Indicates that Flash memory programming has been completed. Writing "0" Clears this bit. Writing "1" Has no effect on operation. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 586

Indicates that the device is in the command input wait state or Flash memory erase is in progress. Reading "1" Indicates that Flash memory sector erase has been completed. Writing "0" Clears this bit. Writing "1" Has no effect on operation. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 587

Indicates that the device is in the command input wait state or Flash memory erase is in progress. Reading "1" Indicates that Flash memory sector erase has failed. Writing "0" Clears this bit. Writing "1" Has no effect on operation. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 588: Flash Memory Status Register (fsr)

Details Reading "0" Indicates that data is being programmed/erased. (Programming/erasing next data is disabled.) Reading "1" Indicates that data has been programmed/erased. (Programming/erasing next data is enabled.) [bit3] Reserved bit Always set this bit to "0". FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 589

Details Writing "0" Maps SA1 to 0x1800-0x1FFF, and the 2 Kbyte address area of SA2 to 0xF800-0xFFFF. Writing "1" Maps the 2 Kbyte address area of SA2 to 0x1800-0x1FFF, and SA1 to 0xF800-0xFFFF. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 590

0x1FFF 0x2000 0x2000 0x7FFF 0x8000 0xBFFF 0xC000 SA2: 30 Kbyte SA2: 32 Kbyte SA2: 14 Kbyte SA2:16 Kbyte 0xF7FF 0xF7FF 0xF800 0xF800 Interrupt SA1: 2 Kbyte SA1: 2 Kbyte vector 0xFFFF 0xFFFF FSR:SSEN=0 FSR:SSEN=1 FSR:SSEN=0 FSR:SSEN=1 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 591: Flash Memory Sector Write Control Register 0 (swre0)

In addition, a reset initializes this bit to "0" (programming disabled). Table of programming function setup bits and their corresponding Flash memory sectors Bit name Corresponding sector in Flash memory SA2E SA1E SA0E MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 592

To program data to or erase data when FSR:SSEN is "1", set SA0E, SA1E and SA2E in the SWRE0 register to "1" first. For details of the sector map of the Flash memory, see Figure 26.2-1 and Figure 26.8-1. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 593: Flash Memory Status Register 3 (fsr3)

This bit indicates whether the Flash memory has malfunctioned or not. bit0 Details Reading "0" Indicates that no malfunction of command input has occurred so far. Reading "1" Indicates that a malfunction of command input has occurred. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 594: Flash Memory Status Register 4 (fsr4)

This bit enables or disables the generation of interrupt requests triggered by the failure of Flash memory chip erase. bit5 Details Writing "0" Disables the interrupt request upon failure of Flash memory chip erase (FSR4:CERTO = 1). Writing "1" Enables the interrupt request upon failure of Flash memory chip erase (FSR4:CERTO = 1). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 595

Indicates that Flash memory chip erase has failed. Writing "0" Clears this bit. Writing "1" Has no effect on operation. [bit3:0] Undefined bits Their read values are always "0". Writing values to these bits has no effect on operation. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 596

Figure 26.8-4 FSR2:PGMTO when Flash Memory Programming Failed Program command Program timeout Reset command FSR:RDY FSR3:PGMS FSR3:SERS FSR3:ESPS FSR3:HANG FSR2:PGMTO Figure 26.8-5 FSR2:ERSEND during Flash Memory Sector Erase Sector erase command Sector erase END FSR:RDY FSR3:PGMS FSR3:SERS FSR3:ESPS FSR3:HANG FSR2:ERSEND FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 597

Figure 26.8-8 FSR2:PGMTO and FSR2:ERSEND when Flash Memory Programming Failed with Flash Memory Sector Erase Suspended Sector erase Sector erase Program Reset Sector erase suspend Program suspend timeout command command command command resume command FSR:RDY FSR3:PGMS FSR3:SERS FSR3:ESPS FSR3:HANG FSR2:PGMTO FSR2:ERSTO FSR2:ERSEND MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 598

Program suspend Reset timeout command command command resume command command FSR:RDY FSR3:PGMS FSR3:SERS FSR3:ESPS FSR3:HANG FSR2:PGMEND FSR2:ERSTO Figure 26.8-11 FSR4:CERTO when Chip Erase Failed Chip erase Reset command command Chip erase timeout FSR:RDY FSR3:CERS FSR3:HANG FSR4:CERTO FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 599

CHAPTER 26 DUAL OPERATION FLASH MEMORY MB95630H Series 26.8 Registers Figure 26.8-12 FSR4:CEREND during Chip Erase Chip erase Chip erase command FSR:RDY FSR3:CERS FSR3:SERS FSR4:CEREND MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 600

(4) Program address Program data Read internal address. Next address Data Data polling (DQ7) Data Execution timeout (DQ5) Read internal address. Data Data polling (DQ7) Data Last address? Program error FSR:WRE Disable Flash memory programming. End of programming FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 601

When Flash memory programming is disabled by setting the WRE bit to "0", no write access to a sector in the Flash memory can be executed even though it has been enabled by setting a bit corresponding to that sector in the SWRE0 register to "1". MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 602: Notes On Using Dual Operation Flash Memory

Flash memory or erasing data from the Flash memory as shown in the examples in Figure 26.5-1 and Figure 26.5-2. The restriction above does not apply if the Flash memory write control program is executed on the RAM. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 603: Chapter 27 Non-volatile Register (nvr) Interface

CHAPTER 27 NON-VOLATILE REGISTER (NVR) INTERFACE This chapter describes the functions and operations of the NVR interface. 27.1 Overview 27.2 Configuration 27.3 Registers 27.4 Notes on Main CR Clock Trimming 27.5 Notes on Using NVR Interface MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 604

Figure 27.1-1 shows the retrieval of NVR during a reset. Figure 27.1-1 Retrieval of NVR during Reset 0x0FE4 0bXXX01010 0x0FE5 0bXXX00001 0x0FE7 0bXXX10101 NVR Interface (I/O Area) 0x0FEB 0b11111111 0x0FEC 0b00000000 0xFFBB 0bXXX10101 0xFFBC 0bXXX01010 (Flash Area) 0xFFBD 0bXXX00001 0xFFBE 0b11111111 0xFFBF 0b00000000 Memory Map FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 605

CRTDA3 CRTDA2 CRTDA1 CRTDA0 WDTH WDTH7 WDTH6 WDTH5 WDTH3 WDTH2 WDTH1 WDTH0 WDTH4 Equal to 0xA5 ? Equal to 0x96 ? Watchdog timer Equal to 0x97 ? WDTL WDTL7 WDTL6 WDTL5 WDTL4 WDTL3 WDTL2 WDTL1 WDTL0 MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 606

Main CR clock trimming register (upper) 27.3.1 CRTL Main CR clock trimming register (lower) 27.3.2 CRTDA Main CR clock temperature dependent adjustment register 27.3.3 WDTH Watchdog timer selection ID register (upper) 27.3.4 WDTL Watchdog timer selection ID register (lower) 27.3.4 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 607: Main Cr Clock Trimming Register (upper) (crth)

Lowest main CR clock frequency See "27.4 Notes on Main CR Clock Trimming" and "27.5 Notes on Using NVR Interface" for details of main CR clock trimming and notes on changing the main CR clock values respectively. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 608: Main Cr Clock Trimming Register (lower) (crtl)

Lowest main CR clock frequency See "27.4 Notes on Main CR Clock Trimming" and "27.5 Notes on Using NVR Interface" for details of main CR clock trimming and notes on changing the main CR clock values respectively. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 609: Main Cr Clock Temperature Dependent Adjustment Register (crtda)

Lowest main CR clock frequency See "27.4 Notes on Main CR Clock Trimming" and "27.5 Notes on Using NVR Interface" for details of main CR clock trimming and notes on changing the main CR clock values respectively. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 610: Watchdog Timer Selection Id Register (upper/lower) (wdth/wdtl)

The hardware watchdog timer is enabled; the software watchdog timer is disabled. The Other than the above hardware watchdog timer keeps operating in all standby modes (stop mode, sleep mode, time-base timer mode and watch mode). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 611: Notes On Main Cr Clock Trimming

Table 27.4-1 Step Size of Main CR Clock Trimming Coarse trimming value Fine trimming value Function CRTH[4:0] CRTL[4:0] To achieve the minimum frequency 0b11111 0b11111 To achieve the maximum frequency 0b00000 0b00000 Step Size 220 kHz to 300 kHz 14 kHz to 20 kHz MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 612

Figure 27.4-1 Relationship between Main CR Clock Frequency and Trimming Step Size (with CRTDA[4:0] = 0b10000) 10000 9000 8000 7000 6000 5000 4000 3000 2000 1000 CRTH[4:0] settings, CRTL[4:0] settings Trimming data (CRTH[4:0], CRTL[4:0]) FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 613: Notes On Using Nvr Interface

2. The trimming value has been preset before this device is shipped. If the preset trimming value is modified after the device has been shipped, Fujitsu Semiconductor does not warrant proper operation of the device with respect to use based on the modified trimming value.
Page 614

CHAPTER 27 NON-VOLATILE REGISTER (NVR) INTERFACE MB95630H Series 27.5 Notes on Using NVR Interface FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 615: Chapter 28 Comparator

CHAPTER 28 COMPARATOR This chapter describes the functions and operations of the comparator. 28.1 Overview 28.2 Configuration 28.3 Pins 28.4 Interrupt 28.5 Operations and Setting Procedure Example 28.6 Register MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 616

"H" if the voltage of the inverting analog input voltage (negative input) is lower than the reference voltage; otherwise, it outputs "L". In addition, upon detection of a rising edge or falling edge of the comparator output, the comparator outputs a corresponding interrupt. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 617

(When CMPn_P and CMPn_N analog input is enabled (VCID = 0), the corresponding GPIO input and output is disabled.) Edge detection circuit (From an external pin) CMPn_P CMPn_O (To an external pin) (From an external pin) CMPn_N Comparator MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 618

(CMR0C:IF) is automatically set to "1" at the same time. The output status of a comparator can be read through the OS bit in the comparator control register (CMR0C). FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 619

Table 28.3-1 shows details of the pins of the comparator. Table 28.3-1 Pins of Comparator Pin name Pin function CMPn_P Comparator non-inverting analog input (positive input) CMPn_N Comparator inverting analog input (negative input) CMPn_O Comparator digital output MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 620

In stop mode, watch mode or time-base timer mode, the edge detection circuit stops operating, and the output edge detection interrupt flag bit (IF) in the comparator control register (CMR0C) will not be updated even if the comparator has been turned on. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 621

2. Activate the comparator according to the settings shown in Figure 28.5-1. 3. Wait until the comparator stabilizes. 4. Clear the interrupt flag bit. (CMR0C:IF = 0) 5. Enable the comparator interrupt request (CMR0C:IE = 1), and enable the comparator output (CMR0C:VCOE = 1) if necessary. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 622

CHAPTER 28 COMPARATOR MB95630H Series 28.6 Register 28.6 Register This section describes the register of the comparator. Table 28.6-1 List of Comparator Register Register Register name Reference abbreviation CMR0C Comparator control register 28.6.1 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 623: Comparator Control Register (cmr0c)

Indicates that an output rising edge/falling edge has occurred. Writing "0" Clears this bit. Writing "1" Has no effect on operation. Note: This bit is not updated in stop mode, watch mode or time-base timer mode. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 624

Disables comparator output. The output pin of the comparator is used as general-purpose I/O port. Writing "1" Enables comparator output. [bit0] PD: Comparator power down control bit This bit powers up or down the comparator. bit0 Details Writing "0" Powers up the comparator. Writing "1" Powers down the comparator. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 625: Chapter 29 System Configuration Controller

CHAPTER 29 SYSTEM CONFIGURATION CONTROLLER This chapter describes the functions and operations of the system configuration controller (called the "controller" in this chapter). 29.1 Overview 29.2 Register 29.3 Notes on Using Controller MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 626

PG2/X1A/SNI2 pin • Selecting the EC0 input pin as the external count clock input pin for the 8/16-bit composite timer • Selecting the 8/16-PPG output ports from P10, P11. P13 to P16 and P62 to P67 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 627

CHAPTER 29 SYSTEM CONFIGURATION CONTROLLER MB95630H Series 29.2 Register 29.2 Register This section describes the register of the controller. Table 29.2-1 List of Controller Register Register Register name Reference abbreviation SYSC System configuration register 29.2.1 MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 628: System Configuration Register (sysc)

Before using the EC0 input function, enable the external count clock input of the 8/16-bit composite timer. For details, see "CHAPTER 11 8/16-BIT COMPOSITE TIMER". bit3 Details Writing "0" Selects P12/EC0 pin as the external count clock input pin. Writing "1" Selects P04/EC0 pin as the external count clock input pin. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 629

SYSC:RSTEN be initialized to "1" in the initialize program routine after a reset for stable operation. With the reset input/output functions having been enabled, all types of reset, including the watchdog reset, can be used. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 630: Notes On Using Controller

While the MPG is in use, the P62 to P67 pins are being used as MPG output pins. In this situation, if it is necessary to use the PPG function, set the PPGSEL bit to "0" to switch the PPG output pins to the P10, P11, and P13 to P16 pins. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 631: Appendix

APPENDIX This section provides an overview of instructions. Addressing Special Instruction Bit Manipulation Instructions (SETB, CLRB) MC-8FX Instructions Instruction Map MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 632: Appendix A Instruction Overview

MC-8FX In the F MC-8FX, there are 140 kinds of one byte instructions (256 bytes on the map), and the instruction code is composed of the instruction and the operand following it. Figure A-1 shows the correspondence of the instruction code and the instruction map.
Page 633

(Whether 8- bit length or 16- bit length is decided by the instruction used.) This shows that the address that contents of x show is an object of the access. ((x)) (Whether 8- bit length or 16- bit length is decided by the instruction used.) MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 634

• S: Become "1" It shows the code of the instruction. When a pertinent instruction occupies OP CODE two or more codes, it follows the following description rules. [Example] 48 to 4F: This shows 48, 49..4F. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 635: A.1 Addressing

APPENDIX A Instruction Overview MB95630H Series A.1 Addressing Addressing MC-8FX has the following ten types of addressing: • Direct addressing • Extended addressing • Bit direct addressing • Index addressing • Pointer addressing • General-purpose register addressing • Immediate addressing •...
Page 636

"Ri" in instruction table. In this addressing, fix one high rank byte of the address to "01" and create one subordinate position byte from the contents of RP (register bank pointer) and three subordinate bits of the operation code to access to this address. Figure A.1-6 shows an example. FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 637

0xFFC4 : 0xFFC5 0xFFC6 : 0xFFC7 0xFFC8 : 0xFFC9 0xFFCA : 0xFFCB 0xFFCC : 0xFFCD 0xFFCE : 0xFFCF Figure A.1-8 shows an example. Figure A.1-8 Example of Vector Addressing CALLV #5 (Conversion) 0xFFCA 0xFE 0xFEDC 0xFFCB 0xDC MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 638

This is used when doing the operation decided by the operation code with the addressing that does not have the operand in the instruction table. In this addressing, the operation depends on each instruction. Figure A.1-10 shows an example. Figure A.1-10 Example of Inherent Addressing Old PC 0x9ABC New PC 0x9ABD FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 639: A.2 Special Instruction

TH (higher 8-bit of the temporary accumulator) before execution of the instruction are not used for the operation. Note that since the instruction does not change the flags, a branch may occur depending on the multiplication result. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 640

Therefore, in Figure A.2-5, the value "0x1235" stored in A corresponds to the address where the following operation code of "XCHW A, PC" is stored. This is why "0x1235" is stored instead of "0x1234". FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 641

CALLV #vct. Accordingly, Figure A.2-7 shows that the value saved in the stack (0x1232 and 0x1233) is 0x5679, which is the address of the operation code of the instruction that follows "CALLV vct" (return address). MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 642

(call instruction) Upper Lower CALLV #7 0xFFCE 0xFFCF CALLV #6 0xFFCC 0xFFCD CALLV #5 0xFFCA 0xFFCB CALLV #4 0xFFC8 0xFFC9 CALLV #3 0xFFC6 0xFFC7 CALLV #2 0xFFC4 0xFFC5 CALLV #1 0xFFC2 0xFFC3 CALLV #0 0xFFC0 0xFFC1 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 643

"1" is always read from this bit during a bit manipulation. This prevents the flag from being cleared accidentally by writing the value "0" to the interrupt request flag bit when manipulating another bit. MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 644

APPENDIX A Instruction Overview MB95630H Series A.4 F MC-8FX Instructions MC-8FX Instructions Table A.4-1 to Table A.4-4 show the instructions used by F MC-8FX. ■ Transfer Instructions Table A.4-1 Transfer Instructions MNEMONIC Operation TL TH AH N OPCODE 1 MOV...
Page 645

APPENDIX A Instruction Overview MB95630H Series A.4 F MC-8FX Instructions Note: In automatic transfer to T during byte transfer to A, AL is transferred to TL. If an instruction has plural operands, they are saved in the order indicated by MNEMONIC.
Page 646

APPENDIX A Instruction Overview MB95630H Series A.4 F MC-8FX Instructions Table A.4-2 Arithmetic Operation Instruction (2 / 2) MNEMONIC Operation TL TH AH N OPCODE 46 AND A, #d8 2 (A) (AL) 47 AND A, dir 2 (A) (AL) (dir)
Page 647: Appendix A Instruction Overview

APPENDIX A Instruction Overview MB95630H Series A.5 Instruction Map Instruction Map Table A.5-1 shows the instruction map of F MC-8FX. ■ Instruction Map Table A.5-1 Instruction Map of F MC-8FX MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED...
Page 648

APPENDIX A Instruction Overview MB95630H Series A.5 Instruction Map FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E...
Page 649

MN702-00009-2v0-E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL 8-BIT MICROCONTROLLER New 8FX MB95630H Series HARDWARE MANUAL June 2013 the second edition FUJITSU SEMICONDUCTOR LIMITED Published Sales Promotion Department Edited...