Fujitsu MB91460 SERIES FR60 User Manual page 358

Chapter 26 DMA Controller
2.DMA Controller (DMAC) Registers
Table 2-2 Settings for Extended Transfer Request Sources
IS EIS RN
10110 0110 102
10111 0110 103
11000 0110 104
11001 0110 105
11010 0110 106
11011 0110 107
11100 0110 108
11101 0110 109
11110 0110 110
11111 0110 111
10000 0111 112
10001 0111 113
10010 0111 114
• When reset: IS4-0 is initialized to 00000
• When reset: EIS3-0 is initialized to 0000
• These bits are readable and writable.
[Bits 19 to 16] BLK3 to 0 (BLocK size): Block size specification
These bits specify the block size for block transfer on the corresponding channel. The value specified by these
bits becomes the number of words in one transfer unit (more exactly, the repetition count of the data width
setting). If block transfer will not be performed, set 01
transfer. The size becomes 1.
BLK
XXXX Block size of the corresponding channel
B
• When reset: Not initialized.
• These bits are readable and writable.
• If 0 is specified for all bits, the block size becomes 16 words.
• During reading, the block size is always read (reload value).
[Bits 15 to 00] DTC (Dma Terminal Count register)*: Transfer count register
The DTC register stores the transfer count. Each register has 16-bit length.
All registers have a dedicated reload register. When the register is used for a channel that is enabled to reload
the transfer count register, the initial value is automatically written back to the register when the transfer is
342
Function
Programmable Pulse Generator 6
Programmable Pulse Generator 7
Programmable Pulse Generator 8
Programmable Pulse Generator 9
Programmable Pulse Generator 10
Programmable Pulse Generator 11
Programmable Pulse Generator 12
Programmable Pulse Generator 13
Programmable Pulse Generator 14
Programmable Pulse Generator 15
ADC 0
res.
res.
.
B
.
B
Function
-
-
-
-
-
-
-
-
-
-
-
-
-
(size 1). This register value is ignored during demand
H
Transfer stop request