Fujitsu MB91460 SERIES FR60 User Manual page 25

■ About access size and bit position
Register name Register mark
(1) Counter control register (Higher byte)
This is the register (higher byte) which controls up/down counter operation.
CCRH0 (Up/down counter 0): address 00B4h (Access: Byte, Half-word, Word)
CCRH1 (Up/down counter 1): address 00B8h (Access: Byte, Half-word, Word)
M16E/Reserved
*
bit15: Enable 16-bit mode
M16E (CCRH0 only)
*: CCRH1: ReservedAlways write 0 for writing. The read value is indeterminate.
When access size changes, bit position changes.
• In the case that address offset value is +0 (Example: CCRH0 register)
Access size
Half-word
Word
• In the case that address offset value is +1 (Example: CCRL0 register)
Access size
Byte
Half-word
Word
• In the case that address offset value is +2 (Example: UDCR1 register)
Access size
Byte
Half-word
Word
• In the case that address offset value is +3 (Example: UDCR 1 register)
Access size
Byte
Half-word
Word
Target peripheral device Address
Enable 16-bit mode
8-bit x 2-channel mode (8-bit mode)
16-bit x 1-channel mode (16-bit mode)
Address
0B4 +0
Byte
H H
0B4 +0
H H
0B4 +0
H H
Bit name
Address
0B4 +1
H H
0B4 +0
H H
0B4 +0
H H
Bit name
Reserved
Address
0B0 +2
H H
0B0 +2
H H
0B0 +0
H H
Bit name
Address
0B0 +3
H H
0B0 +2
H H
0B0 +0
H H
Bit name
Access size
07 06 05
15 14 13
31 30 29
M16E CDCF CFIE
07 06 05
07 06 05
23 22 21
CTUT UCRE
07 06 05
15 14 13
15 14 13
D15 D14 D13
07 06 05
07 06 05
07 06 05
D7 D6 D5
Chapter 1 Introduction
4.How to Use This Document
Bit position
Initial value
Attribute
Bit position
04 03 02
12 11 10
28 27 26
CLKS CMS1 CMS0
Bit position
04 03 02
04 03 02
20 19 18
RLDE UDCC CGSC
Bit position
04 03 02
12 11 10
12 11 10
D12 D11 D10
Bit position
04 03 02
04 03 02
04 03 02
D4 D3 D2
01 00
09 08
25 24
CES1 CES0
01 00
01 00
17 16
CGE1 CGE0
01 00
09 08
09 08
D9 D8
01 00
01 00
01 00
D1 D0
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