Operation - NEC UPD703116 User Manual

9.2.5 Operation

(1) Operation in general-purpose timer mode
TM1n can perform the following operations in the general-purpose timer mode.
(a) Interval operation (when ENMD bit of TMC1n register = 1)
TM1n and CM1n0 always compare their values and the INTCM1n0 interrupt is generated upon
occurrence of a match. TM1n is cleared (0000H) at the count clock following the match. Furthermore,
when one more count clock is input, TM1n counts up to 0001H.
The interval time can be calculated with the following formula.
Interval time = (CM1n0 value + 1) × TM1n count clock rate
(b) Free-running operation (when ENMD bit of TMC1n register = 0)
TM1n performs full count operation from 0000H to FFFFH, and after the TM1OVFn bit of the STATUSn
register is set (to "1"), TM1n is cleared to 0000H at the next count clock and resumes counting.
The free-running cycle can be calculated with the following formula.
Free-running cycle = 65536 × TM1n count clock rate
(c) Compare function
TM1n connects two compare register (CM1n0, CM1n1) channels and two capture/compare register
(CC1n0, CC1n1) channels.
When the TM1n count value and the set value of one of the compare registers match, a match interrupt
(INTCM1n0, INTCM1n1, INTCC1n0
operation, TM1n is cleared upon generation of the INTCM1n0 interrupt.
Note This match interrupt is generated when CC1n0 and CC1n1 are set to the compare register mode.
(d) Capture function
TM1n connects two capture/compare register (CC1n0, CC1n1) channels.
When CC1n0 and CC1n1 are set to the capture register mode, the value of TM1n is captured in
synchronization with the corresponding capture trigger signal.
Furthermore, an interrupt request signal (INTCC1n0, INTCC1n1) is generated by the valid edge of the
INTP1n0, INTP1n1 input signals specified as the capture trigger signals.
CHAPTER 9 TIMER/COUNTER FUNCTION
Note
, INTCC1n1
User's Manual U14492EJ5V0UD
Note
) is output. Particularly in the case of interval
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