NEC UPD703116 User Manual page 562

32-bit single-chip microcontrollers

Table of Contents

(11) CAN global interrupt pending register (CGINTP)

The CGINTP register is used to confirm the pending status of MAC error interrupts.

This register can be read/written in 8-bit units.

Cautions 1. When "1" is written to a bit in the CGINTP register, that bit is cleared (to 0). When "0"

is written to it, the bit's value does not change.

2. An interrupt is generated when the corresponding interrupt request is enabled and

when no interrupt pending bit has been set (to 1) for a new interrupt.

The correct or incorrect timing of setting the interrupt pending bit (to 1) is controlled

by an interrupt service routine. The earlier that the interrupt service routine clears the

interrupt pending bit (to 0), the more quickly the interrupt is generated without losing

any new interrupts of the same type.

The interrupt pending bit can be set (to 1) only when the interrupt enable bit has been

set (to 1). However, the interrupt pending bit is not automatically cleared (to 0) just

because the interrupt enable bit has been cleared (to 0).

Use software processing to clear the interrupt pending bit (to 0).

For details of invalid write access error interrupts and unavailable memory address access error

interrupts, see 11.14.2 Interrupts that are generated for global CAN interface.

Bit position

Note xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable

peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being

m = 2, 6, A, E

CHAPTER 11 FCAN CONTROLLER

Indicates that a wake-up interrupt from CAN sleep mode with stopped clock supply to

FCAN is pending.

0: Not pending

Indicates that an invalid write access error interrupt is pending.

0: Not pending

Indicates that an unavailable memory address access error interrupt is pending.

0: Not pending

User's Manual U14492EJ5V0UD

Initial value