NEC UPD703116 User Manual page 221

Figure 9-2. Block Diagram of Timer 0 (Mode 2: Sawtooth Wave)
BFCMn3
CM0n3
Clear
1/1
16
f
1/2
XX
TM0n
1/4
f
f /2
1/8
XX CLK
1/16
1/32 16
BFCMn0
CM0n0
BFCMn1
CM0n1
BFCMn2
CM0n2
Remarks 1. TM0n:
CM0n0 to CM0n3:
BFCMn0 to BFCMn3: Buffer registers
DTRRn:
DTMn0 to DTMn2:
ALVTO:
ALVUB:
ALVVB:
ALVWB:
2. n = 0, 1
3. f : Internal system clock
XX
4. f : Base clock (40 MHz (MAX.))
CLK
CHAPTER 9 TIMER/COUNTER FUNCTION
INTCM0n3
DTRRn
R
DTMn0
S
R
DTMn1
S
R
DTMn2
S
Timer register
Compare registers
Dead-time timer reload register
Dead-time timers
Bit 7 of TOMRn register
Bit 6 of TOMRn register
Bit 5 of TOMRn register
Bit 4 of TOMRn register
User's Manual U14492EJ5V0UD
Output control by
external input (ESOn),
TM0n timer operation
ALVTO
12
Underflow
R
S
R
S
ALVUB
Underflow
R
S
R
S
ALVVB
Underflow
R
S
R
S
ALVWB
TO0n0
(U phase)
TO0n1
(U phase)
TO0n2
(V phase)
TO0n3
(V phase)
TO0n4
(W phase)
TO0n5
(W phase)
221