NEC UPD703116 User Manual page 338

32-bit single-chip microcontrollers

Table of Contents

(5) Timer 2 time base control register 0 (TCRE0)

The TCRE0 register controls the operation of TM2n (n = 0, 1).

This register can be read/written in 16-bit units.

When the higher 8 bits of the TCRE0 register are used as the TCRE0H register, and the lower 8 bits are used

as the TCRE0L register, they can be read/written in 8-bit or 1-bit units.

Cautions 1. If ECREn = 1 and ECEEn = 1 have been set, it is not possible to input an external clear

signal (TCLR2) for TM2n. In this case, first set CLREn = 1, and then clear TM2n by

software (n = 0, 1).

2. When clearing is performed using the ECLR signal, the TM2n counter is cleared with a

delay of (1 internal count clock set with bits CSEn2 to CSEn0 of the CSE0 register) + 2

base clocks. Therefore, if external clock input is selected as the internal count clock,

the counter is not cleared until the external clock (TI2) is input.

3. The ECREn bit and the ECEEn bit cannot be set to 1.

4. If the ECEEn bit is set to 1 and the ECREn bit is set to 0, a down count operation cannot

be performed.

5. When UDSEn1, UDSEn0 = 01 and OSTEn = 1, the counter does not count up when the

counter value is 0. Therefore, when the counter value is 0, set OSTEn = 0, and after the

value of the counter ceases to be 0, set OSTEn = 1. Also, on the application, change the

value of OSTEn from 0 to 1 using the sub-channels 0 and 5 interrupt signals.

6. When the TM2n count value is cleared (0) by setting CLREn to 1, the CLREn = 1 setting

must be held for at least one of the internal count clocks set by the CSEn2 to CSEn0

bits of the CSE0 register.

Example When timer 20 (TM20) is cleared (0)

CHAPTER 9 TIMER/COUNTER FUNCTION

<1> Select f

/2 as TM20 internal count clock

<2> Clear (0) the TM20 count value

<3> Set the conditions required for the TM20 count clock

<4> Start the TM20 count operation

User's Manual U14492EJ5V0UD