(4) TO0n0 to TO0n5 output timing
Figure 9-46. TO0n0 to TO0n5 Output Timing in PWM Mode 0 (Symmetric Triangular Wave), PWM Mode 1
(Asymmetric Triangular Wave)
TM0CEn bit
CM0n3
CM0nx
TM0n
0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H
DTRRn
DTMnx
FFFFH
f
CLK
Match signal
F/F
TO0n0, TO0n2,
TO0n4
TO0n1, TO0n3,
TO0n5
Remarks 1. The above figure shows the timing until the compare register and the TM0n timer match and the
TO0n0 to TO0n5 outputs change.
2. x = 0 to 2
3. n = 0, 1
4. f
: Base clock
CLK
CHAPTER 9 TIMER/COUNTER FUNCTION
0008H
0003H
0008H 0007H 0006H 0005H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H
0002H
0002H
0001H 0000H
User's Manual U14492EJ5V0UD
FFFFH
0002H 0001H 0000H
FFFFH
291